================================================================================ IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ================================================================================ Attendees from February 26, 2020 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Intel Corp. Michael Mirmak*, Ifiok Umoh Keysight Technologies Radek Biernacki Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SiSoft Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* Michael Mirmak convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Michael called for review of the minutes from the February 19, 2020 meeting. Randy Wolff moved to approve the minutes. Bob Ross seconded. The minutes were approved without objection. Review of ARs: - Michael to ask Steve Parker what is the preferred method for communicating files to be posted. - Michael noted Steve is not a subscriber to the email list. Steve had questions on how to name some of the files. Michael will request Steve to subscribe to the mailing list [AR]. - Randy to update his example to show the different methods for modeling extended nets. - Randy reported he sent out an updated version with more examples. We can review this. Michael asked if this includes an example of a stacked die. Randy noted we would have to discuss this. Bob noted it would be helpful to have, but the content of this example could apply to a stacked die. Randy commented the syntax would be very similar. Bob noted the bondwires might go to the base layer, and the IBIS-ISS will determine how they are wired up. Michael thought this should be easy, but we can defer the discussion. Opens: - Michael noted, on March 5, DASC will be having a face to face meeting in the Bay Area. He plans to attend the meeting and expects there to be discussion on interconnect related to the IEEE 2401. Michael asked if there was any message that we should convey. EMD Conversion Example from BRD File: Walter Katz gave an overview of the process for creating an EMD. He noted the board file used is a JEDEC reference DIMM board. He imported the .brd file and converted to a native database, which is a spreadsheet format. The spreadsheet has the CAD net reference designators, pin numbers, and part numbers, which can be used to create the EMD. The EMD was generated programmatically. Walter can also read that EMD file into the tool. He commented the main issue is the rail voltages. Michael asked about the reference designator map and if we can list the fields in a comment line. Walter agreed we can do this. Michael noted this could be added to the specification examples. Walter took the EMD pin list and listed the number of component connections and the part numbers which would be the IBIS files. He did not generate the spice files and used shorted models in some cases. Arpad Muranyi asked if it is possible to pass in parameters to the IBIS-ISS files. Walter noted this can be done similarly to the Interconnect syntax, but he did not do that in this case. Walter noted the QVREF is classified as a rail net, despite not having voltages applied in the database. Walter stated the QVREF is not hooked up to the connector, and these are supplied internally on the board. Randy commented the QVERF are supplied by the Register as the reference. Walter stated the issue is that the rail needs to be created inside the EMD. Walter noted one of the other issues is with resistor models, which may be series, pullup, or pulldown resistors. The pullup resistors could be connected to different rails. For power aware simulations, the resistors need to be connected to the rails; alternatively, we could have the resistors connect to voltage sources. But, there is nothing in the EMD syntax which sets the voltage for the rails. The series resistors could be connected with IBIS models. You could also have an Rpower IBIS model to connect the resistor to the VTT. In Walter's example case, there were no voltages specified in the .brd file. Michael asked if the EMD needs to supply this voltage information. Walter noted, if there is a resistor in the EMD, the connections need to be specified. If we want to automatically connect the resistor to a voltage source, the tool would need to know the value. Walter did a count on the number of pins, and there are a lot of resistors that connect to VTT for instance. If you want a power distribution model for VTT, you would need a terminal for each resistor. This would be a large number of terminals. He would like to be able to connect every terminal with a bus_label to short them together. For power aware simulations, it would be very useful to connect multiple designators as one terminal. Walter suggested we should have a way to connect the voltage values and have the nominal rail voltage values supplied by the EMD. Walter summarized the issues: 1. Designators point to part numbers and part numbers to IBIS files 2. Connecting across interfaces to short terminals 3. Supplying rail voltages Bob asked about the connections across interfaces. Walter noted there could be many interfaces and there is no way to short them all together. Michael asked if the word interface means the interface in a 3D field solver. Bob noted the interface is the designator component. Walter noted, in his example, there are 620 designators, and Bob classifies these as interfaces. Bob commented the IBIS terminator models can supply the voltages, and this could be used for the resistor models. Walter agreed this can work for terminators, but not for resistors that are not connected to the rails. Bob stated these can use series resistor models. Walter noted this could work, but for the series resistors of extended nets you would have to look at each resistor and determine the type of model to create for it. Randy noted there could also be more complicated clock differential terminators. Walter noted there are multiple issues when considering how to generate the model and the needs for both power aware and non power aware simulations. Randy commented VTT is a complicated network. Bob noted VTT could be internally generated. Randy noted VTT terminates many types of signals. There are banks of resistor packs and individual resistors which connect to VTT. And, VTT has an internal plane. The rail is supplied from the edge connector by the mother board. Walter noted he would model the PDN with two terminals for each side of the board and some small R, L, and C. But, to do this in EMD, we would need to have the ability to short the terminals. Walter to summarize the issues and send them out in email [AR]. Michael asked if we should add these to the bin list. Bob was concerned that this would undercut the routing by shorting things, and we would need to think about how to do this to include the details. Bob suggested to move the IBIS-ISS parser to a tabled topics list. Next Meeting: The next meeting will be March 4. Bob moved to adjourn. Randy seconded. The meeting adjourned without objection. ================================================================================ Bin List: EMD Comments to be Resolved: (See BIRD202.1 tracking spreadsheet) IBIS-ISS Parser: - IBIS-ISS parser scope document