================================================================================ IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ================================================================================ Attendees from March 4, 2020 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Intel Corp. Michael Mirmak*, Ifiok Umoh Keysight Technologies Radek Biernacki Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SiSoft Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* Michael Mirmak convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Michael called for review of the minutes from the February 26, 2020 meeting. Walter Katz moved to approve the minutes. Bob Ross seconded. The minutes were approved without objection. Review of ARs: - Michael to request Steve Parker to subscribe to the mailing list. - Michael is still working with Steve to get documents posted. He was not sure if Steve is on the mailing list yet. - Walter to summarize the issues related to EMD PDNs and send out in an email. - Walter reported he has sent this out. Opens: - Michael will send the task list from the February 18 meeting [AR]. EMD PDN Issues: Walter noted the first issue is a suggestion to map Part Numbers, .ibs, and .emd file names together. The issue is that the model creator has to map the part numbers to the .ibs files while writing the EMD. Walter stated the other issue is to add a new section for rail voltages to define typ, min, and max values. The EDA tool can make use of these and correlate to the IC corner. Randy Wolff asked if these rails would be at the edge connector or are internally generated sources. Walter replied it could be both, and different rail voltages could have different corners. If you are not doing power aware simulations, this can be a convenient way to connect termination and pullup voltages. Walter commented the last item is the ability to connect designators with a bus_label. This can be accomplished with a bus_label of *.VSS. This could also be done for a VTT rail with separate left side, right side, and edge connector terminals. The model can be between these terminals with a relatively simple power aware circuit. Michael asked about the item #1 and if organization by the component keyword would be sufficient. Walter replied, for a DIMM, you might have 8 DRAMs and 100 resistors, with many having the same part number. These would point to specific components. Randy noted it is different if we want the component to be the same as the part number, as the new approach would allow for mapping the two. Michael asked, for the rail voltages, if the idea is similar to auto assignment based on net names. Is this to identify the expected voltages. Walter replied the issue is that some databases have the rails defined. But, in the cases when it is not defined, the tool has to make an educated guess, and the user will have to verify the values. Randy asked if this is optional or required. Walter suggested to make it optional, but he strongly recommends it. Michael stated his concern would be about the wire that carries the voltage and the voltage supply definitions. If this is a cross check, that is okay, but if it is to define voltages for the simulator, we need to be careful. Walter agreed we would need some language to define what happens when you have a source for the voltage. Bob asked if this keyword acts as an alternative to externally supplied voltages. Most tools allow the user to switch in a voltage source or have the model supply the voltage. Walter commented the IBIS file has voltages which define the measurement conditions for the corners. Bob noted we can create different cases with external voltages and corner cases. Walter agreed his approach is the same idea. Randy commented this is useful information. Bob asked about the .ebd files mentioned in item #1, as we do not to use .ebd in .emd. Randy agreed we decided to not allow use of .ebd in .emd. We did not want to create problems connecting the two formats. Michael suggested we should check this in the draft. Bob commented the designator is a part as distinguished from the part number. Each resistor would have a different reference designator, and each of these could point to the same IBIS file. Randy noted we still have the designator list, but you are pointing to a part number. Bob asked which component is being used and how this is specified. Walter noted two different .ibs files could have the same component name. We may need some clarification for item #1 to say unique IBIS file and component name. Bob asked if we would consider the same change to EBD. Michael stated we are not considering changing EBD. Walter noted EBD is limited to one set of connections between the EBD and the components. But, for EMD the models can be much more complicated, and this syntax change can make it easier to create and maintain the EMD models. Randy agreed this can be useful. Bob asked if there is a list of standardized part numbers. Walter replied the part number is just a string. Michael asked if we are only including the part number in the EMD and not the IBIS file. Bob asked why we need a part number. Walter noted you can use an arbitrary part number. Randy noted it is useful for automating the creation of the EMD. Randy showed the board database used to create Walter's EBD example. There are many package symbols and device types, which could be used to map to the .ibs file. Bob noted another option would be to have both options in the syntax. Walter noted the idea is to automate the generation of the EMD file and limit the manual work to write EMD file. Bob noted, on item #4, this can be good way to short the pins. He asked, for item #4c to allow shorting all pins, if it would be illegal to call the rail VSS and U1.VSS if they exist on one terminal. Walter replied it would be illegal to have *.VSS and U1.VSS. Bob asked about VSS only. Walter replied this would not be illegal since this would be on the connector side and short all of the connector VSS. Michael asked if Walter would generate the BIRD text associated with these suggested improvements [AR]. Walter asked if Michael can send the latest EMD draft [AR]. Walter will not be able to attend next weeks meeting. Next Meeting: The next meeting will be March 11. Randy moved to adjourn. Bob seconded. The meeting adjourned without objection. ================================================================================ Bin List: EMD Comments to be Resolved: (See BIRD202.1 tracking spreadsheet) IBIS-ISS Parser: - IBIS-ISS parser scope document