================================================================================

IBIS INTERCONNECT TASK GROUP
https://urldefense.proofpoint.com/v2/url?u=http-3A__www.ibis.org_interconnect-5Fwip_&d=DwIGAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=DcQR-qLpQg5lIreuM6-NYECRIAFXt268PRNS5WO043M&m=KXAdbWLIXIepE-jlyWi0x87wMqBTgNJnZUrhDP7_UQcQ9VvzpuuB9ZAmc1LCd11w&s=FFSW9RH0A3L0SvkuG397sf8xPe9YbhEBSny92cS2Khs&e=  
Mailing list: ibis-interconnect@freelists.org 
Archives at https://urldefense.proofpoint.com/v2/url?u=http-3A__www.freelists.org_archive_ibis-2Dinterconn_&d=DwIGAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=DcQR-qLpQg5lIreuM6-NYECRIAFXt268PRNS5WO043M&m=KXAdbWLIXIepE-jlyWi0x87wMqBTgNJnZUrhDP7_UQcQ9VvzpuuB9ZAmc1LCd11w&s=zq64IYrbu__aryT7fTjetEKRsWFJPFjD5veW7YzZhQY&e=  

================================================================================

Attendees from March 23, 2022 Meeting (* means attended at least using audio)

ANSYS                                Curtis Clark
Intel Corp.                          Michael Mirmak
                                     Michael Brownell*
Marvell                              Steve Parker
MathWorks                            Walter Katz*
Micron Technology                    Justin Butterfield*
                                     Randy Wolff*
Siemens EDA                          Arpad Muranyi*
ST Microelectronics                  Aurora Sanna
Teraspeed Labs                       Bob Ross*
University of Illinois               Jose Schutt-Aine
Zuken USA                            Lance Wang*


Michael Brownell from Intel introduced himself.  He is working on interconnect 
development for data center applications.


Randy Wolff convened the meeting.  No patents were declared. 
Justin Butterfield took minutes.


Review of Minutes:
- Randy called for review of the minutes from the March 16, 2022 meeting.  
  Randy displayed the minutes.  Arpad Muranyi motioned to approve the 
  minutes.  Bob Ross seconded.  The minutes were approved without 
  objection.


Review of ARs:
- Walter Katz to send out the Port Naming Enhancement for Touchstone Files 
  slides.
  - Done.  Randy noted there were additional offline edits.

Opens:
- None


Discussion:

Port Naming:
Walter asked if we need both logical name and physical name columns.  Arpad 
suggested this is necessary.

Walter would like feedback on the reference information.  We could add another 
table for the reference information, but we need to discuss this.

Walter noted Chord Signaling, where we have 3 or more wires, is another 
discussion point.  He suggested we could add another column with the Chord 
signal as a mechanism for grouping the ports.  Arpad suggested we could use 
the differential column in the case of Chord Signaling.  We want to have the 
ability to associate more than 2 wires to support Chord Signaling.  

Randy asked about automatically generating the IBIS Interconnect and EMD 
formats from the Touchstone file.  He also asked about supporting Chord 
Signaling in IBIS with a new Diff Pin keyword.  Walter stated we also want the 
port naming to work without IBIS.  With the port naming information, you can 
create a schematic symbol automatically.  This can be done independently of 
IBIS.  Arpad added there are limitations in IBIS to support Chord Signaling.  

Arpad noted that there are two scenarios to consider for logical names or 
physical names.  In the first case, the connections are known, such as a DIMM 
or a package.  In the other case, such as a cable, you do not know what you 
are connecting the model to.  He suggested we need to support both scenarios.  
Arpad commented the concern is the difference between the outside and inside 
terminal naming for a DIMM, for instance.  Walter commented, for a DIMM, the 
pins have to match for the device component and map to the pins on the PCB.  
Arpad stated the names of the ports could be different in this syntax vs. in 
the IBIS syntax the pin numbers are consistent.  Walter noted the pin name is 
a physical pin location that is referred to as the pin number in the 
industry.  Arpad commented the connections should be done by the pin number, 
while the logical name is not known.  Walter stated, if you have multiple 
slots on a PCB with daughter boards plugged into each slot, this can be 
handled by the EDA tool.  Walter added that you can give a designator for the 
external interface.  You could give the physical name as only the pin name 
without the designator.  Arpad agreed this could work.

Randy asked about the package model case, where we have buffer, pad, and pin 
locations.  Walter replied that you could have pin.1, pad.1, buffer.1.  The 
names would be dependent on the application.  Arpad stated we have the 
qualifiers of Pad_I/O, Pin_I/O, Buffer_I/O, etc. that we need to consider.  


Arpad motioned to adjourn.  Bob seconded.  The meeting adjourned.


Next Meeting:
The next meeting will be March 30.


================================================================================
Bin List:
1. Touchstone 3
2. Pole-residue support for Touchstone
3. ISSIRD process
4. Port naming
5. TSIRD format