====================================================================== IBIS INTERCONNECT TASK GROUP http://www.eda.org/ibis/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Wednesday, April 9, 2014 8 AM US Pacific Time Objective: produce a unified package improvement proposal (BIRD) for consideration by the IBIS Open Forum that satisfies industry package modeling requirements Thanks to Arpad Muranyi for acting as guest chair this week. Thanks also to Mike LaBonte for the teleconference assistance. Agenda: 1) Roll call 2) Call for patent disclosures 3) Opens 4) Review of ARs 5) Complete review of IC vendor examples (A. Muranyi) - Can the SiSoft proposal universal/default examples be duplicated in the BIRD163-165 approach? - Do we want to support pre-layout package information in IBIS? - Are there any features or situations where the proposals significantly differ (particularly a structure that cannot be described) - Which value is more important: re-use of existing IBIS keywords/structures or simplicity of format? Audio: ====== Voice dial-in: (800) 637-5822 International: +1 (647) 723-3937 <--- (For Canada) 0114501530 <--- (For Sweden) 0201400572 <--- (For Sweden Toll Free) 069509594672 <--- (For Germany) 08001014542 <--- (For Germany Toll free) Access Code: 685-0440 Mentor Global Crossing Teleconference commands for audio: http://www.globalcrossing.com/customer/collaboration/cust_ready_access_tips.aspx Web: ==== Topic: IBIS Interconnect Task Group Date: Every Wednesday, from Wednesday, April 9, 2014 to no end date Time: 11:00 am, Eastern Daylight Time (New York, GMT-04:00) Meeting Number: 732 254 400 Meeting Password: IBIS ------------------------------------------------------- To join the online meeting (Now from mobile devices!) ------------------------------------------------------- 1. Go to https://sisoft.webex.com/sisoft/j.php?MTID=m5eb6350fa87ac02fdb9827351400351f 2. If requested, enter your name and email address. 3. If a password is required, enter the meeting password: IBIS 4. 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To view this type of rich media files in the meeting, please check whether you have the players installed on your computer by going to https://sisoft.webex.com/sisoft/systemdiagnosis.php. --------------------------------------------------------------------- MEETING MINUTES Wednesday, April 2, 2014 Attendees denoted by * Agilent Technologies - Radek Biernacki* Altera - David Banas* Cadence Design Systems - Brad Brim* Intel - Michael Mirmak* Mentor Graphics - John Angulo*, Arpad Muranyi*, Andrey Matvienko* Micron Technology - Justin Butterfield*, Randy Wolff* Signal Integrity Software - Walter Katz Teraspeed Consulting Group- Bob Ross* No patents were declared. No opens were declared. Arpad Muranyi began reviewing his remaining examples from the last meeting, focusing on power and ground. In SiSoft’s proposal, pad.vss and pad.gnd are used to denote rail connections, with [Die Supply Pads] keyword. Mentor's version uses [Node Declarations]. Michael Mirmak asked whether the rules of [Node Declarations] have changed to allow or require all die pads to be declared under the keyword. Arpad confirmed this was part of the new proposal. Specific ports are named for package models with connecting terminal. [Pin Mapping] creates similar rules to [Node Declarations]. Bob Ross noted that the external terminal names will still follow the old [Node Declarations] rules. In the Mentor proposal, two [Circuit Call] keywords are used, with each mapping from ports by name to pin names under [Pin]. In the second [Circuit Call], on-die nodes map from the buffer to the gcref and pcref terminals of the instances associated with the pins. Colon notation is new, and part of the official BIRD. One reserved name, power_bus, is not included in the BIRD, while puref, pcref are reserved names; [Pin Mapping] bus names are stated. John Angulo observed that there are both explicit uses of [Pin Mapping] and examples where it is not used. The use of colon vs. dot notation is arbitrary. Radek Biernacki noted that he preferred the colon to dot. [Circuit Call] listing in the second column maps to ports list in [External Circuit] *by position*. Radek suggested this is redundant; we don't need to reshuffle the presentation of the nodes. Arpad agreed, but noted that he was trying to keep usage of older keywords. Radek added that he was not suggesting a change, but a replacement or add-on might be needed. Arpad stated that there was a great amount of overlap between two proposals, but some differences too. Arpad showed new examples, based on SiSoft's proposal where no equivalents yet exist in Mentor's approach. [Begin ISS Model] uses a name from the [Model] name; Ports map based on models. Michael asked whether packages and models are associated in lockstep? John Angulo stated that there may be a pin/model order of precedence. Pin_Default defines a default package for the entire device. Randy Wolff noted that, when memory modules are designed, they have to handle multiple memory components, with different packages; the module involves time-delay matching to all the signals. Creating special models involves putting in package parasitics that are the same for every pin. The model authors don't want to put the differences into the module, which is the same for every combination. This is where a single S2P applies, per Walter Katz's example, with sliding. Arpad asked whether this sliding approach requires too much work to use it. Randy replied that the use of a W-element but with different lengths sounds more like a pre-layout model. John added that coupling is an issue, and that he understood that this approach applies in pre-layout only. One situation to consider is if a pre-layout design has 3 driver I/O symbols sitting in it, and the tool looks for a matching package model in a drag-and-drop approach. Arpad noted that no equivalents exist to his knowledge yet for this sliding approach in the BIRD 163-165, etc. proposals. He would like feedback on whether this is worth doing, if [External Circuit] approach is not favored. Radek mentioned previous interest (2 years ago) in using [External Circuit] with IBIS-ISS, where the [External Circuit] applies generally with an S2P; John believes this is possible.