====================================================================== IBIS INTERCONNECT TASK GROUP http://www.eda.org/ibis/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from July 08 Meeting (* means attended) ANSYS Curtis Clark* Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak Keysight Technologies Radek Biernacki* Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* Signal Integrity Software Walter Katz, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Arpad Muranyi led the meeting. No patents were declared. Walter requested discussion of comments received from Brad Brim. Arpad noted that Michael Mirmak is the interconnect BIRD editor, and that we would not make modifications to it during this meeting. ARs: Randy Wolff to send diagrams to the reflector for review. This was done. These can be used as needed in the new interconnect BIRD. Local/global Ground: Walter said It is now unanimous that C_comp should connect to local ground, not node 0. The conclusion from yesterday is that nothing will be done about legacy models. Model makers have the ability to produce models that do not use node 0> Brad agreed the effect depends on the power delivery network used. We will not disallow node 0 in IBIS-ISS subcircuits. We may want a warning for this if we ever have a parser. Radek said we need to have that check at some point. Mike L said we have three parsers. Brian Andresen wrote TSCHK. He was not sure who wrote ICMCHK. ISS checking could be added to IBISCHK. Bob asked if Brian would be able to write ISSCHK. Radek said this was not likely, but was not sure. Bob said ICMCHK was written by Lynne Green's husband. Walter said he had run a simulation where the near and far ends of a W-line used different references. This worked fine, giving the same voltages at the receiver. It was no surprise that the noise on the planes was small, because planes are good conductors. He also tried using two connected W-lines. This worked well in all simulators he tried. The reference point between the lines had 1V on it. Walter said Brad Brim got 30V for the same test. Brad had agreed it would be an awful imposition to rule out node 0 for making subcircuits. Radek said That is not what node 0 is for. He said every tool will arrive at a solution, but they may be inconsistent. Walter said there would be no measurable benefit getting rid of node 0. Radek said you need to tie one node in each circuit to some specific potential node. It can be any potential value. He said Brad had been trying to convince us that global ground should not have to be the local ground. Walter said that a pulldown resistor should never be hooked up to node 0. Radek said the local ground can be connected to global ground externally. He also said it is OK if everything is connected to global ground. Arpad reminded that the question is where C_Comp is connected to. The package may have a ground plane, but the PCB can be trickier. He suggested imagining a package model with a ground pin and ground pad, asking where does that ground go to? Walter said a memory chip may have VSS and VSSQ planes, and the addr/cmd nets and DQ nets must pass over the correct planes. He said we have to assume this, but we don't really know how the package is constructed. Radek said that historically there has been an assumption that signals at the pad have been referenced to ideal ground, and that this was not correct. Walter said we can't do anything about legacy models. Radek said we need to identify all of the port to port relationships, and that analog ground terminal should be available. He noted that there is no C_pkg, the nodes are pin and pad. Walter said that these changes will have to go into IBIS 6.2, and that this should be discussed Friday in the Open Forum meeting. Bob said that if a W-line with N conductors is wrapped in an IBIS-ISS subcircuit and all W terms are brought out, there are 2*N terminals, and that the reference is a conductor. Arpad said the reference might not be considered a conductor. Radek said that a W-line with 4 signal lines will have 5*2 terminals for 8 ports. Walter agreed that a W-line with 4 signals will have 10 terminals, with two terminals being used for the reference. Bob said one of those terminals might for example be connected to pin VSS and the other PAD VSS. Radek said there can be an unreliable potential at that point, noting that for S-parameters you have N ports plus one reference. Arpad asked why we did not include initial conditions for IBIS-ISS? Radek said that would make a difference for signals that are relative to Pulldown_reference. Mike noted that the wishlist at the end of ATM minutes has one item: "ISS simulator directives". Radek said this is a separate issue from a general simulator directive capability. Arpad asked if we should standardize the syntax for this. Walter said IBIS-ISS does not have to be included in final simulation deck directly, because the syntax for directives can differ from one simulator to another. Bob said vendors can do anything they want with IBIS-ISS content, including adding non-ISS elements to implement the functionality. Radek said he would rather have initial conditions expressed as subcircuit parameters.