================================================================================ IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ================================================================================ Attendees from July 31, 2019 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SiSoft Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* Michael Mirmak convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Michael called for review of the minutes from the July 24, 2019 meeting. Randy Wolff moved to approve the minutes. Bob Ross seconded. The minutes were approved without objection. Review of ARs: - Mike LaBonte to have the Touchstone survey results posted to the website. - Michael reported he has not seen this on the website yet. Opens: - Michael has a couple EMD technical questions to discuss and would like to review the bin list. EMD Review: Bob noted one issue is if we want a component pin list. Walter Katz commented there are two ways to connect the rails. One method is to have a component pin list. The other method is to look into the component model and connect by the pin_name. Walter noted he has resolved Randy's case where VDD and VDDQ may be connected separately in the package. The resolution was to specify the terminals separately for the component while on the module they may be a single terminal. Walter has added this capability to draft 10 of the document. Michael asked if the connection was done by signal_name. Walter replied the signal_name is not used but one terminal can connect to one or more pins. Bob commented this is a special case and we should not upset our syntax for this special case. Randy suggested to view the example in draft 10. Michael suggested pictures of the examples would be greatly helpful. Walter noted, in the last EMD example, terminal 6 has multiple pin names. The idea is multiple component pins can be assigned to one terminal. Arpad Muranyi asked if there is any limitation on the number pin_names. Randy noted the line length limit is 1024 characters. Arpad stated the pin_names could be more complicated, and we could reach the line length limit. Bob suggested model makers can short the PDN terminals. Randy disagreed that we should not make things more difficult for model makers to create these models. Bob asked why the example does not use signal_name VSS to connect the terminals. This way you need only to specify one value. Arpad asked how the other VSS component connections know they are connected. Walter noted the EDA tool would have to look at inside the component. Randy commented this information is in the pin list and pin mapping information. Bob suggested to use the signal_name in the component as a way of collapsing the pin_names to one terminal. Walter commented the problem with this is that the DIMM database only has packages and pin numbers. This is populated with parts and the names of the signals may be different across vendors. He suggested it is a bad practice to connect by signal_name. Bob stated different EMD models could be created for each vendor. Walter stated this would result in too many combinations in the case when memory, register, and PLL vendors are all be different for a DIMM. Arpad asked about the signal_name meaning that we now have in IBIS and if it applies to EMD. Walter noted the terminals are not necessarily shorted but that they are connected with a low impedance path. Two terminals that have the same signal_names have a low impedance path. Arpad asked which pins we need to list and if we can assume the other pins are shorted. Bob noted he does not like the syntax, since we do not collapse the terminals into the signal_names. Walter suggested to move on and discuss the other open issues. Michael reviewed the open EMD issues. One of the remaining issues is the naming of "signal_type". Bob suggested to change this to "signal_tag". Walter suggested for Bob to make a motion on this. Michael asked if changing to "emd_signal_type" resolves the issue. Walter replied Bob's issue is with the word "type". Bob strongly recommended to not use the word "type". Michael asked about the file structure issue in the bin list. Bob replied we can drop this issue. Arpad suggested to take a look at the minutes to clarify this issue. Randy took an AR to look at the minutes to determine if any action is required on the EMD "file format structure" issue [AR]. Michael asked about the issue on the number of [Module] keywords allowed per EMD file. Bob had submitted a motion on this to allow more than one [Module] keyword per file. Walter stated we need to have a vote on this. Michael asked about the bus_label issue. Walter replied the bus_label issue is resolved. Walter commented the [EMD Designator Map] keyword has been moved in the document, but we still have to do an editorial review. Michael suggested we have a debate on the component pin list issue. Bob to put his EMD related motions in writing in the form of an email [AR]. Walter suggested to fix the typo in the example and Michael to send out the document. Michael will send out the fixed version of the EMD document [AR]. Next Meeting: The next meeting will be August 7. Walter moved to adjourn. Randy seconded. The meeting adjourned without objection. ================================================================================ Bin List: EMD Comments to be Resolved: 1. Proposal to rename signal_type 2. Number of [Module] keywords allowed per EMD file. 3. Proposal to remove the subparameter "emd_" prefix. 4. Resolve if [Component Pin List] is required. IBIS-ISS Parser: - IBIS-ISS parser scope document