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IBIS INTERCONNECT TASK GROUP
http://www.eda.org/ibis/interconnect_wip/ 
Mailing list: ibis-interconnect@freelists.org 
Archives at http://www.freelists.org/archive/ibis-interconn/ 
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Attendees from August 5 Meeting (* means attended)
ANSYS                                                               Curtis Clark*
Cadence Design Systems                              Bradley Brim
Cisco                                                                 David Siadat
Intel Corp.                                                        Michael Mirmak*                       
Keysight Technologies                                   Radek Biernacki*
Mentor Graphics                                             Arpad Muranyi*
Micron Technology                                        Justin Butterfield*, Randy Wolff*
Signal Integrity Software                              Walter Katz*, Mike LaBonte*
Teraspeed Labs                                               Bob Ross*
University of Aveiro in Portugal                  Wael Dghais       

No patents were declared.  No opens were raised.  The discussion focused on the alternative proposals 
for the “Terminal” structure in the draft Interconnect BIRD.

Bob Ross shared his examples of Terminals, in contrast with the existing format.  He suggested 
eliminating the “Terminal” word in lines, specifying the number of terminals explicitly.  “Number” is 
maintained, ahd location, name_type, and name are provided.  He added new designation, 
“Pin_A_rail”.  Everything in the list other than Name is a reserved word. Terminal numbers must be 
sequential, and even Name can contain a reserved word.

Walter Katz commented that the example lists contain A_puref, then signal_name, then DQS; what does 
it mean?
Bob noted that the signal name is DQS, referring to the pullup reference connection on DQS.
Walter observed that A_puref is on the buffer side.  His recent “elevator speech” e-mail was intended as 
an introduction or quick summary of the basic points of the interconnect format.  

Bob stated that Signal connections can use the pin name or the signal name.  The rules suggest one can 
skip terminals, or list them out of order.  The highest number given must match the total number of 
Terminals given (not sure about this rule).   Radek Biernacki observed that S4P has five terminals and an 
S-element declaration has 5 terminals.

Bob suggested that the default power and ground voltages come from the IBIS model.  Walter added 
that you can also have a separate subcircuit for power distribution.  Pin VSS and Buffer VSS would be 
specified separately, with all the VSS on the package shorted together; all the VSS on the silicon shorted 
together on another node.  With VDD, that would be a 4-terminal distribution system.  Randy Wolff 
confirmed that this is a possible way.

Bob’s second existing example does not show power rails either.  Walter noted that, in the first 
example, you would need a second subcircuit for your power distribution, with a separate terminal list.

For VDD, the interconnect is between VDD pins and die VDD pads.  Of the 8 terminals shown, 5 are 
signal pins and 3 are pad signal names (which are VDD rails).  “Pin_A_signal” here is “Pin_rail” under 
Bob’s approach.  “Rail” is either a signal name or a pin name.

The list must contain either a specific buffer or a specific signal name.  Walter noted that IBIS is clear 
that signal_name is the databook name.  VDD has a certain value, VDDQ has a certain value.  These are 
separate networks.

Arpad Muranyi’s proposals were not discussed.  These will be addressed in a later meeting.  Walter 
accepted the AR to provide alternate versions of the draft examples using the simplified format based 
on Bob’s suggestions.

ARs
Walter Katz - to provide the proposal document’s examples using the new format, for discussion
Michael Mirmak - to send out Interconnect draft 22 as written - DONE