====================================================================== IBIS INTERCONNECT MODELING TASK GROUP MEETING MINUTES AND AGENDA http://www.eda.org/ibis/adhoc/interconnect/ Mailing list: ibis-interconn@xxxxxxxxxxxxx ====================================================================== Next Meeting Wednesday, August 25, 2010 9 AM US Pacific Time Telephone Bridge Passcode 916-356-2663 4 488-9692 (for international and alternate US numbers, contact Michael Mirmak) LiveMeeting: https://webjoin.intel.com/?passcode=4889692 Agenda: - Attendees - Call for patents - Opens - IBIS-ISS Comments Review and live editing ====================================================================== Minutes from August 18: Attendees: ---------- (* denotes present) Agilent - Radek Biernacki*, John Moore, Ken Wong Ansoft - Denis Soldo Cadence Design Systems - Terry Jernberg, Brad Griffin Cisco Systems - Mike LaBonte Green Streak Programs - Lynne Green Hewlett-Packard - Rob Elliott IBM - Greg Edlund* ICT-Lanto - Steven Wong* Intel - Michael Mirmak* Mentor Graphics Corp. - Arpad Muranyi*, John Angulo*, Vladimir Dmitriev-Zdorov Micron Technology - Randy Wolff*, Justin Butterfield* Sigrity - Sam Chitwood, Raymond Y. Chen, Tao Su, Brad Brim* SiSoft - Walter Katz* Teraspeed Consulting Group - Bob Ross* ======================================================================== No patents were declared. During opens, Bob Ross asked whether IBIS-ISS can call other subcircuits. Michael Mirmak replied that the top-level ISS file is assumed to consist of a subcircuit, with nested subcircuits possible within it. Radek Biernacki added that, if ISS files may be included within an ISS file, all the contents should be ISS conformal. This means that the specification may have to distinguish top-level files from included files. The basic choice is whether to check all files OR check only top-level files against ISS rules. Arpad Muranyi responded that an alternative would be to make the top-level ISS file a subcircuit, while each included file could use ISS syntax but not include subcircuits. Randy Wolff suggested an alternative approach: any parser should just parse the top-level file, assuming that the top-level file would be "flattened". The parser, if run on an included file, should notify the user that "this isn't a complete file; please parse the top-level file." Walter Katz explained that the top-level could have multiple subcircuit definitions; also, the .subckt and matching .ends statements could be split across include files. This would only be "seen" by the parser when the flattened file was parsed. In the interests of time, Michael moved ISS conversation to the next meeting. He added that Synopsys had responded positively to the IBIS-ISS editing efforts and that their technical leads had provided additional advice on interpreting line and equation continuations (+ vs. /) Brad Brim reviewed the MCP 1.1 document and showed a physical example of MCP. He noted that all pins associated with nets or a single electrical node are grouped together. Every physical pin is documented, then grouped. For example, in a system with 3 signals, 5 power connection points and 1 ground Connection point, the MCP description would include 9 nets total: 9 board-side connections but lots of connections at the die side. Brad also showed a text/file example. Walter asked about linkage between different types of MCP description (board, package, etc.). Brad responded that you don't necessarily know what order the pins and netlist will use; names and physical locations will guide you in ordering the pins to associate the pins electrically. Walter compared this to a package instance, such as U17, which has a part number in the CAD database. MCP would map the part number to CAD database number. Brad replied that, like IBIS, a reference designator in a physical layout will map to a particular instance of an IBIS model. John Angulo compared this to something like EMD, where the IBIS file component is associated with a reference designator. The decision to connect them is up to the EDA tool in MCP to let the user make a connection. He asked whether a one-click solution would be possible. Walter suggested there are as many package models as the user wishes to create. The user would not want to create one package model for the whole thing; rather, the user/maker looks at only a particular set of nodes or connections for which to create a model. Brad suggested that most users are likely SI engineers, doing chip, package or board connections. Suggestions on the draft document should be directed to Brad or the reflector. The team will begin edits in the next MCP-oriented meeting. ------------------------------------------------------------------ The IBIS Ad Hoc Interconnect Task Group Mailing List Archives are available at: http://www.freelists.org/archives/ibis-interconn TO UNSUBSCRIBE: Send a message to "ibis-interconn-request@xxxxxxxxxxxxx" with a subject of "unsubscribe" To administer your subscription status from the web, visit: http://www.freelists.org/list/ibis-interconn