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IBIS INTERCONNECT TASK GROUP
http://www.eda.org/ibis/interconnect_wip/ 
Mailing list: ibis-interconnect@freelists.org 
Archives at http://www.freelists.org/archive/ibis-interconn/ 
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Attendees from August 26 Meeting (* means attended)
ANSYS                                               Curtis Clark
Cadence Design Systems                              Bradley Brim
Cisco                                               David Siadat
Intel Corp.                                         Michael Mirmak*
Keysight Technologies                               Radek Biernacki
Mentor Graphics                                     Arpad Muranyi*
Micron Technology                                   Justin Butterfield*, Randy Wolff
Signal Integrity Software                           Walter Katz*, Mike LaBonte*
Teraspeed Labs                                      Bob Ross*
University of Aveiro in Portugal                    Wael Dghais

No patents were declared.  No opens were raised.  

Walter Katz summarized recent discussions on pre-layout support, including Arpad Muranyi’s note to 
the reflector on cases where there is *not* 1-to-1 mapping between pins and buffers.  The team came 
to the conclusion last week that we would not support pre-layout interconnect or package models.

Arpad clarified that “pre-layout” refers to components, without complete package/interconnect (just a 
subset that can apply to any group of pins and pads).  Walter replied that a model may be referred to by 
name or function.  

IBIS doesn’t support 1 buffer connecting to 2 pins or 2 buffers connecting to 1 pin.  The new package is 
now limited to 1-to-1.  The task is to complete this proposal, then extend EBD.  No changes are required 
to the proposal to state 1-to-1 mapping.  

Bob Ross reminded the team to keep series pins in mind.  Arpad asked whether this proposal should co-
exist with existing older syntax.  Bob Ross suggested that, for [External Circuit], it should.  For pre-layout, 
the proposal might use reduced set of power and ground.  Walter suggested considering the modern IP 
case as pre-layout.  

Michael Mirmak noted that the BIRD161 approach is incomplete.  Walter responded that the first 
process in creating a library is to associate an IBIS file with a part number.    Michael disagreed.

Walter reviewed his terminal proposal update.  The critical aspects are:
Pin name/number
Signal name/databook number
Pad name
Aggressor

The power nets are assumed to all be shorted together.

Bob suggested one consideration, to add pad names.  Additional team discussion focused on whether 
pads should have names.  
The current syntax supports individual and all-shorted connections.  Eight different connection options 
are supported.  However, non-shorted and shorted connections for the same rail are *NOT* supported.  

Walter reminded the team that bus names are signal names.  Vendors may be using Buffer Rail Mapping 
instead of Pin Mapping.  

ARs
Bob Ross to submit to the meeting or reflector an alternate proposal on reflector addressing pads, 
potentially using Pin Mapping