====================================================================== IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from August 30 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki, Ming Yan Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Mike LaBonte convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Mike called for review of the minutes from the August 23 meeting. Mike noted a clarification in his AR regarding the Terminal line rules that the minutes should indicate BIRD189.5 draft 5 rather than just BIRD189.5. Walter Katz moved to approve the minutes. Bob Ross seconded. The minutes were approved without objection. Review of ARs: - Bob to draft a rule in regards to how [Pin Mapping] interacts with BIRD189.5. - Bob reported that he needs to think about it more. He is considering proposing a statement that [Pin Mapping] and bus_labels may collide. - Bob and Mike to add language about unused terminals in the Terminal line rules. - Mike reported that this is not yet done. - Walter commented that Arpad Muranyi's proposed changes to Terminal line rules would address this. Opens: - Arpad had submitted a motion over email about Terminal lines. Walter had seconded this motion. Walter would like to discuss these changes further. BIRD189.5 Referencing: Michael Mirmak asked if there are any additional topics needed to cover on referencing. Bob replied that the issue remains, since there are no dedicated references as only VSS nodes are passed through. Walter commented that we pass in rail voltages and those rail voltages can be used as the references internally. He added that the reference must be passed in to the model. Bob asked about ISS signal models that do not include a power rail or ground rail. Walter replied that [Pin Mapping] gives the implied rails. Arpad asked about the case of a [Pin] list with only signals. Walter replied that in that case you have to use the ideal ground node 0 as the reference, since that is all you have. Michael stated we should exclude model cases which are not intended for power delivery simulation from the discussion. Walter commented that for every voltage there needs to a local reference with which it is measured against. Arpad suggested to add a statement that Power Aware models should include at least one power and ground pin. Bob commented that the wording should be less specific in case of a -5V supply instead of ground as an example. Walter suggested that the [Pin] list should contain at least one ground pin. Arpad thought that it could be a power or ground. Walter clarified that this is only a suggestion and that if the model does not have these pins then the reference would be node 0. Michael gave an AR to Walter and Arpad to look into if the current syntax will support using node 0 as the reference and propose language if it does not. Bob requested that they contact Brad Brim and Radek Biernacki with their proposal as well. Walter commented that in BIRD189.5 we are not defining the way in which models should be created, but rather the way they are wrapped for IBIS. BIRD189.5 Incomplete Paths: Arpad commented that, in regards to the issue of missing models in the path, we do need to add some language to the BIRD. Bob commented that, in regards to [Pin Mapping] if pad to pin is missing, then there is a dead short. Walter commented that package models go from pin to die pad, in which case the on die interconnect affects are included in the buffer [Model]. BIRD189.5 gives model makers the option to include the on die interconnect in an Interconnect Model. Arpad stated the real question is if the pad to pin model is missing, how the rules of precedence should be applied to the legacy model. Walter agreed that the legacy model should be used in this case. He stated that the EDA tool should not short pad to pin, but rather use the legacy models. Bob stated that the precedence issue is when the model makers include coupling for some pins but not others. In [Define Package Model], you have coupling to everything, but in [Interconnect Model]s, you may have coupling to only some nets. The issue is how [Define Package Model] interacts with the [Interconnect Model]. Walter stated that you should not mix and match BIRD189.5 and [Define Package Model]. Model makers should assume the EDA tool will use one model or the other. Bob agreed. He stated that if the pin to pad segment was not included, the next package model in the hierarchy is [Define Package Model]. Walter commented that it is not worthwhile to document every case of bad models. Arpad moved to adjourn. Mike seconded. The meeting adjourned without objection.