====================================================================== IBIS INTERCONNECT TASK GROUP http://www.eda.org/ibis/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from Sept. 9 Meeting (* means attended) ANSYS Curtis Clark* Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais No patents were declared. No opens. Arpad Muranyi moved to approve the minutes of the previous meeting. Curtis Clark seconded. Minutes were approved without objection. Mike LaBonte suggested that approval was needed for the minutes of the Aug. 26 minutes. Michael Mirmak will ensure these are posted. During the review of ARs from the last meeting, Michael noted that both Walter Katz and Bob Ross had posted their proposals regarding Terminal notation to the Interconnect reflector. Mike LaBonte had posted the presentations to the Interconnect web page. Bob reviewed his proposal. Walter noted that previously the proposal had buffer rail mapping, but that we have pin rail mapping instead of buffer rail mapping now. With this, we can have terminals using bus labels instead of signal names. Walter has updated his BIRD to reflect this. Bob noted that his updated proposal makes his approach and Walter’s more in alignment. A key change is that pad names are not needed as a qualifier anymore. The major aspects: there are buffers, pads and pins. Pin name, signal name and bus label qualifiers are used, as is “aggressor”. There is no pad label in Bob’s list of interconnections. Walter responded that, in an example arrangement, he can have four pins that are VDD; 2 are on bus label VDD1, 2 are on bus label VDD2. He could have a model with one terminal for VDD1 pins, and one terminal for VDD2 pins. Both terminals would be pin rail, while one would use bus label VDD1 and the other would be VDD2. Walter disagrees with the pad description notation used by Bob. Bob noted that he is preparing a document for the EPEPS conference/summit. Walter noted that page 5 of Bob’s presentation shows the same number of pads as pins. In the [Pin Mapping] section, you only have pin names and no pads names. Bob explained his many-to-one and one-to-many support flow. This approach is for power/ground rails and not signal pads/pins. Mike noted that he does not believe the proposals are easy to understand without having matching examples and diagrams. Michael asked where the “center of gravity” of the proposals is, assuming that [Pin] is the center of gravity for IBIS today. Bob replied that terminals define electrical interconnect models. A secondary focus is shorted connections to allow pin mapping. Walter noted that the center of gravity is terminals, asking whether we want to support one terminal with shorted pins. He noted that pin rails will have all VDDs shorted together. We need to have a pin rail with multiple pins tied to the same pad. We also have to treat pins the same as bus supply rails/labels. There is no assumption of 1-to-1 mapping of bus supply pins and pads. We need a column for pad names (really for supply pad names). Bob asked whether we should modify [Pin Mapping] to add a pad name designation. We can do this with just bus labels. AR: Bob to update his proposal with many-to- one and one-to-many examples for pads and pins for supplies. The meeting encountered some audio issues. Via chat and audio, Mike moved to adjourn. Walter seconded.