From: ibis-interconn-bounce@freelists.org on behalf of Mirmak, Michael Sent: Tuesday, September 22, 2015 3:01 PM To: IBIS-Interconnect (ibis-interconn@freelists.org) Subject: [ibis-interconn] Minutes, IBIS Interconnect Task Group Meeting - Sept. 16, 2015 ====================================================================== IBIS INTERCONNECT TASK GROUP http://www.eda.org/ibis/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from Sept. 16 Meeting (* means attended) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki* Mentor Graphics Arpad Muranyi Micron Technology Justin Butterfield, Randy Wolff Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais No patents were declared. Mike LaBonte moved to approve the minutes of the September 9 meeting. Walter Katz seconded. The motion carried with no objections. Walter moved to approve the minutes of the August 26 meeting. Bob Ross seconded. The motion carried with no objections. No opens were raised. Bob noted that he updated his presentation to add pad names as a qualifier. His syntax already supports many-to-one and one-to-many power connections. There are three ways of describing a name: buffer, pad, pin as a location; with that, four qualifiers. Through [Pin Mapping], we can associate many-to-one or one-to-many. If we go with pad/die pad name associations, we can go with a bus label associated with several die pad names. Michael Mirmak asked whether the associations are for power/ground, not for signals. Bob replied that this was correct. Additionally, common bus labels should be considered as on-die shorts. Physically, that’s where they would occur. We can extend common names into other locations, without getting bogged down into other names. Pads and pins (locations) are possible as well. We want to combine electrical terminals like SPICE. AR: Bob to assemble diagrams for these examples. Walter stated that he finds Bob’s proposal confusing and not understandable. He asked Bob to explain the exact case that Bob’s proposal can do that Walter’s cannot. One example has a terminal at a pin, another at the pad, and another at the buffer. Bob responded that he was trying to merge the proposals to be very crisp about the syntax. He has added a qualifier, pad name, to the table. Tentatively, this is the die supply pad. Walter and Bob differ on bus labels. Bob can connect directly from pin to buffer (page 13 of his proposal). Walter asked how many terminals were on this subcircuit. He counts 14: 2 pad terminals, 6 pin terminals, 6 buffer terminals. Pin terminals connect to the PCBs, while buffer terminals connect to buffers. He stated that the pads do not need to be exposed to the EDA tool. Bob replied that coupling could be involved. Radek Biernacki agreed. An in-circuit probing approach or syntax is needed. Walter asked what the pads get hooked up to. Radek responded that we may have the new C_comp structure to support. Walter suggested that two different interconnect models would be involved in that case. Bob stated that this is a capability to enable one subcircuit for the entire path. Michael added that this was a case of probe-ability of connections vs. how a SPICE subcircuit definition is written. Walter answered that there is no sense to make this one subcircuit and expose the pads as part of the standard. Michael asked whether multiple buffers to multiple signal pads to a single pin are supported as connections. Walter answered that these were not supported. Walter added that is is not a bad idea to have probes available at the pads, but not the pads themselves. We should only expose the things which will be connected to something else. Bob suggested probing can be done without exposing the pads. He can accept that limitation now, but does not like technical restrictions generally. Walter added that he does like the probe capability suggested by Radek. Walter presented his e-mail from Sept. 16. Bus labels refer to signal pins. All must be unique and cannot conflict with any existing signal name. Bob suggested this repeats what Pin Mapping does. Walter asked in response how he would associate a component with 4 buffers with each having its own bus label, eventually connecting to a single VDD and single VSS pin. Bob replied that there’s a point there. Walter noted that pins, buffers, and die pads should be split up but that would not be inconsistent with Pin Mapping. AR Walter: will take Terminal section he has been maintaining, will update it with rules. He cannot attend next week. AR Mike: generate pictures/diagrams for relevant examples. Mike moved to adjourn; Walter seconded. The meeting adjourned.