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IBIS INTERCONNECT TASK GROUP
http://www.eda.org/ibis/interconnect_wip/   
Mailing list: ibis-interconnect@freelists.org 
Archives at http://www.freelists.org/archive/ibis-interconn/ 
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Attendees from Sept. 17 Meeting
Intel Corp.				     Michael Mirmak*					
Keysight Technologies                        Radek Biernacki
Mentor Graphics                              Arpad Muranyi*
Micron Technology                            Justin Butterfield*, Randy Wolff*
Signal Integrity Software                    Walter Katz*
Teraspeed Labs                               Bob Ross*

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Minutes from Sept. 17 meeting

No patents were declared. No opens were raised.  Michael Mirmak got the AR to post drafts 10 and 11 of the Interconnect proposal to the website.

The following required work items related to Interconnect proposal are assigned with the progress shown:

1) Address [Pin Mapping] relationship (Michael) 
2) Pre-layout vs. post-layout notation (Walter) - to be added
3) Rules of precedence for different package modeling methods (Walter) - to be added
4) Interaction with Circuit Call and External Circuit (Arpad) - to be added; in progress
5) Unused Terminal text (Brad) - to be checked
6) Die Supply Pads (Walter) - the text is new in Draft 8 and needs review
7) Examples on page 15 in red to be removed (Walter) - to be checked
8) Define Package Model - to be rolled into rules of precedence.
9) Formatting and editorial work on the final draft (TBD)  

Michael presented his summary of how [Pin Mapping] works in IBIS 6.0 and its relationship to the current Interconnect proposal.  

Arpad Muranyi asked if the buses are shorted on the pad side and not the pin side.  Bob Ross observed that the bus rail, if shorted, would override the package definition keywords.  Walter Katz noted that it's a fair assumption that all tools use the approach that package models and Pin Mapping interact, with package paths from the pins still connecting between the pads and pins.

Michael asked whether the buffer supply points on the die are connected together as shorts.

Walter replied that, for example, there are two ways of connecting a pullup:
1) Terminal X goes to buffer Y's pullup
2) Terminal X goes to signal name Vdd (on the buffer side)

The distinction is between buffer, pad, and pin side.  There is a resistance, for example, between the die pad and buffer terminals.  Problem occur when you don't have all the Vdd pads shorted together.  

Walter suggests that his BIRD for Pin Mapping would replace "ideal short" with "connection" in the text.  

Bob replied that we could replace IBIS Pin Mapping with new definition for the new Interconnect proposal.
Walter noted that this would be almost identical to Pin Mapping.  Pin Mapping text should replace "connected with an ideal short" with "connected.  Connected means a low-impedance path..."  

Walter further suggested not using bus names, which should be ignored.  The signal names should be used to signify common rails.  Arpad responded that signal name has no connectivity meaning in IBIS; it's always an arbitrary name.  He cited pages 24/25 in the specification, specifically pins 11 and 12.   

Key question for the team: does Signal_name have a special meaning?  

Walter suggested getting rid of ideal short in pin mapping.  If two pins have the same Signal_name, they are shorted.  Arpad prefers not to change the meanings of the Pin Mapping columns.  

Michael stated that the specification for interconnect needs an alternative to Pin Mapping and clarification of Pin Mapping's treatment/relationship to the new interconnect.

Arpad asked where "the short" is, if we have an on-die interconnect.  There are three landing points that could be shorted: pin, pad, terminal.  Terminal is the buffer pad in traditional IBIS.  The specificaiton needs to differentiate between them.

Michael noted that traditional IBIS doesn't have terminals per se, and we can't short pins.  Bob agreed that nothing shorts pins.  Pads can be shorted through buses under Pin Mapping.  

Arpad suggested that an ISS subcircuit could be used to connect pads and terminals.

The team will reconvene in two weeks to discuss the remaining ARs and any revisions to the proposal.