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IBIS INTERCONNECT TASK GROUP
http://www.eda.org/ibis/interconnect_wip/    
Mailing list: ibis-interconnect@freelists.org  
Archives at http://www.freelists.org/archive/ibis-interconn/  
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Agenda for Sept. 30 Meeting
Review of Attendees
Call for Patents
Review of Previous Meeting Minutes: Sept. 23, 2015
Opens
Review of Walter Katz’s Draft 23 BIRD proposal changes (Terminal)
Review of Mike LaBonte’s updated diagrams
Review of Bob Ross’s updated diagrams


Attendees from Sept. 23 Meeting (* means attended)
ANSYS                                Curtis Clark
Cadence Design Systems               Bradley Brim
Cisco                                David Siadat
Intel Corp.                          Michael Mirmak*                       
Keysight Technologies                Radek Biernacki*
Mentor Graphics                      Arpad Muranyi*
Micron Technology                    Justin Butterfield*, Randy Wolff*
Signal Integrity Software            Walter Katz, Mike LaBonte*
Teraspeed Labs                       Bob Ross*
University of Aveiro in Portugal     Wael Dghais       

No patents were declared.  

Mike LaBonte  moved to approve the minutes of the September 16 meeting.  Bob Ross seconded.  The 
motion carried with no objections.

No opens were raised.   

Bob and Mike shared their diagrams explaining various examples and approaches under the new 
interconnect BIRD proposal 

In Mike’s diagrams, subcircuits are in boxes, pads are in blue, pins are in green, and vertical lines are for shorts.  Drawings only have pullup and pulldown supplies shown (no clamps).  One example, the first, shows an organization only by pin name.  Examples use 5 powers, 5 grounds.   Power/Ground and I/O 
pins are not distinguished by color.

Earlier, terminal content used a box and circuits were points, in essence.  Radek Biernacki noted that no 
ground is explained or mentioned here, in the sense of the more complex non-ideal ground.  

Exact connections are not shown.  Michael Mirmak asked whether P1, P2, and P3 were associated 
(shorted) by signal_name?  Randy Wolff suggested this is an association (not a connection).
Example #2 uses signal_name as a bus name.  Arpad Muranyi noted that we cannot be sure how the tool 
knows the P1,P2,P3 are shorted.  How are the buffer-side pullup and pulldown shorts accomplished?

Example 3 uses Pin Mapping.  Radek noted that this implies Pin Mapping is required for Example 2, but 
not present, for the buffer-side short circuit.  Arpad asked how one can determine whether the red 
short is on the pad side or the buffer side based on the language?

Mike commented on the difficulty of the syntax vs. diagram creation, and the lack of actual circuit 
details in the diagrams.  He will add these circuit information diagrams

Bob showed his own presentation on diagramming.  Pin Mapping associates buffers with pins and 
pads.  We cannot use labels due to confusion.  We instead need to use pin and pad names.   Some 
discussion ensued about simplification of Pin Mapping associations.

For next time, Bob and Mike are to prepare “cleaned up” proposals and diagrams.  

Arpad moved to adjourn.  Radek seconded the motion.