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IBIS INTERCONNECT TASK GROUP
http://www.eda.org/ibis/interconnect_wip/
Mailing list: ibis-interconnect@freelists.org
Archives at http://www.freelists.org/archive/ibis-interconn/
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Attendees from October 21 Meeting (* means attended)
ANSYS                                                        Curtis Clark*
Cadence Design Systems                          Bradley Brim
Cisco                                                         David Siadat
Intel Corp.                                                Michael Mirmak*                      
Keysight Technologies                             Radek Biernacki
Mentor Graphics                                     Arpad Muranyi*
Micron Technology                                 Justin Butterfield, Randy Wolff
Signal Integrity Software                        Walter Katz*, Mike LaBonte*
Teraspeed Labs                                       Bob Ross*
University of Aveiro in Portugal             Wael Dghais      
 
No patents were declared. During opens, Bob Ross mentioned that slides for the Interconnect update at the EPEPS summit were now available.   Walter Katz noted that he had to leave the meeting early.  He added that a presentation on “connecting Pads to Supply Terminals” had been sent out on Saturday.
 
Michael Mirmak called for approval of the Oct. 14 meeting minutes.  Mike LaBonte moved to approve; Arpad Muranyi seconded.  The motion carried without objection.
 
Walter reminded team that there will be no meeting Oct. 28 due to EPEPS.  Meetings will resume the following week.
 
Walter presented some updated slides.  He noted that there are three ways that die pads can interface to terminals: by signal (1 terminal), by die pads (3 terminals), and by bus labels (9 terminals).
Bob asked about the pin name on the buffer, or pullup reference on the pin name.  A bus label has the least granularity, as it will short out all signals with same bus label.
 
Bob added that he has some more detailed questions, but these will be discussed offline.  Walter noted that he had no slides to show “cross cases” (cross connections).  Bob has general concerns on how we define bus labels, as the labels should only come out of how Pin Mapping works and no other source.  Walter responded that there are cases that don’t work if Pin Mapping is the only source of bus labels. 
 
Michael Mirmak asked if it is sufficient to have the parser check for consistency.  Bob replied that the developer would have to write a loop for indirection checking between the keywords.   
 
Michael asked whether Pin Mapping is needed or Bus Labels are an alternative.  Bob responded that one can possibly get by without Pin Mapping, or one can use it, or one can exclude bus labels.  Walter added that Pin Mapping is required to get the correct signal name-to-buffer PU, PD, association. 
 
Bob noted that Walter’s proposal is a combination of both Bus Labels and Die Supply Pads.  In today’s syntax, Bus Label is misused in Draft 24 today, as it extends to signal names but in that case, we do not name die supply pads.  Die Supply Pads would be the superset.  We don’t need one of those keywords. 
 
Mike LaBonte accepted the AR to post Walter’s slides.
 
Michael reviewed Draft 24.  The changes focus mainly on clarifying in-line vs. separate Interconnect models. 
Bob suggested that the extension “ipkg” is inappropriate, as Interconnects are not just for packages; need a generic phrase.  Three letters only would be nice.
 
Bob added that the header for Interconnect Model needs Copyright and other keywords, and should be specified in a separate Chapter.  This Interconnect Model chapter/section would be separate from Package chapter, and the header rules need to be at the top of the section.  A table of keywords needed for Interconnect, as already exists for Packages.