================================================================================ IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ================================================================================ Attendees from October 23, 2019 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SiSoft Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* Michael Mirmak convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Michael called for review of the minutes from the October 16, 2019 meeting. Bob Ross moved to approve the minutes. Walter Katz seconded. The minutes were approved without objection. Review of ARs: - Randy Wolff to create a stacked die EMD model example with power rails. - Michael noted we still need some discussion on this. - Randy to propose some rules for the merged pin cases. - Michael noted we need further discussion on this as well. Randy agreed. Opens: - None. EMD Merged Pins: Michael asked if Randy had finished the review of his example in the last meeting. Randy replied we got through most of his example, but we did not finish the discussion on Arpad Muranyi's email regarding the merged pins issue. Arpad stated this discussion was not finished, and he thought we identified some short comings in the EMD BIRD. But, we need to address these issues in the BIRD text. Walter stated one key item is to address how to do simple rail connections. He has two example cases we need to support. The first example is a module where we do not care about the PDN in the module, but we want to supply power to the components. All of the VDD are shorted on the module, and all of the VDD pins on each component are shorted. There is a terminal for each of these interfaces. The other example is to short all the interfaces into one terminal. This is important functionality, and the syntax should support these cases. Michael asked about the definition of EMD and the recursive nature of the module. Walter gave an example of a DIMM with stacked die. The stack of 4 die is represented by an EMD and there are instances of the stacked model on the DIMM EMD. We want to have the PDN model subcircuit with terminals to the DIMM and one terminal to each designator. When the subcircuit connects to the pins at each interface, it shorts them. Michael asked who controls what is shorted, if it is the person writing the EMD for the DIMM or the EMD for the stacked die. Walter stated it is the person writing the interconnect model for that particular level. Bob noted we group things currently at the EMD interface. We can use signal_name to short all the pins, and the same can be done at the designator interface. This is as far as we should go, but we should add bus_label breakouts of the rails. Walter will add the signal_name and bus_label capability to tie all the pins to a single terminal [AR]. He will add the case if you have a terminal of signal_name, which says all of the pins that match the signal_name are tied to one terminal. If you have a bus_label that matches a signal_name, all pins with that signal_name and no bus_label will be shorted. Bob commented the syntax could use the qualifier of the designator and the signal_name or bus_label to make these connections, and this would be an additional rule to discuss. Walter stated this would cover Randy's case of VDDLL, where he wanted to have the bus_lable on this pin only and use signal_name for all the other pins, which had no explicit VDD. Bob stated there is no limitation that bus_lable has to be different from the signal_name, as it is already distinguished by the qualifier. The entries can default to a bus_label of the signal_name when no bus_label is specified. He proposed this as an additional rule and to match BIRD182. Walter to add EMD bus_label by default rules to match BIRD182 [AR]. Walter noted there is a concept of merged pins in EMD. There is the ability to have multiple nets with the same signal_name but two pin_names to short them. Bob stated we no longer have the rule that the signal_name has to be the same across multiple interfaces. Randy stated the issue is when you are using the pin_name qualifier. If you use signal_name, you short all the pins. In the case where you use the pin_name, but you only define some of the pins, there is an issue of what to do with the undefined pins. The EDA tool needs to make some assumptions to connect the terminals of the model. Walter stated you could have the same issue with bus_label. Bob suggested to not connect unspecified pins, since they are not defined. He suggested to not define a large list of pins. Bob also suggested to have model makers use bus_labels to connect the terminals. Arpad asked what happens if the model maker only connects some of the VDD pins. Walter suggested to use the connections that are specified and leave the other connections floating. Michael asked if this addresses the issue. Arpad would like to see this written in the BIRD with some examples. Walter to add merged pin example cases to the EMD BIRD [AR]. Bob asked about the use of VSS in each of the Randy's example models but no connection to the VSS nodes for the designators. Arpad suggest to use A_gnd for ideal ground connections. Bob noted, in the example, there is no VSS path to each of the designators, and the model would have VSS as a floating node. Walter commented, since VSS is defined to the DIMM, it would be connected this way. Walter noted, for W-elements, you may want to have a VSS terminal at both ends. Randy stated, if you want signals with an ideal reference, this would work. Michael asked if this resolves all of the issues. Bob replied there is still some confusion. He agrees with using A_gnd when you want ideal ground. In Randy's example, VSS is only at the designator and does not specify the path of the VSS rail. This gets into the connections vs. shorts definitions. We need to make sure it is clear there is no VSS by default. Walter commented that the state of the art for power aware simulations is to use ideal ground. If you want more sophisticated simulations, you should have separate connections at each interface. And, we are not limited in the syntax to only use ideal ground. Michael suggested to focus on the draft changes, and we can discuss the VSS connections further in the next meeting. Michael stated he cannot host the meeting next week. Randy and Justin cannot attend next week. Bob moved to cancel the meeting next week. Walter seconded the motion. There were no objections. Next Meeting: The next meeting will be November 6. Walter moved to adjourn. Arpad seconded. The meeting adjourned without objection. ================================================================================ Bin List: EMD Comments to be Resolved: 1. Should the [Define Module] keyword be renamed? - RESOLVED 2. Documentation of CAD nets, extended nets and signal names definitions. - RESOLVED 3. Add bus_labels as possible Terminal_type_qualifiers. - RESOLVED 4. Add [End EMD Pin List], [End Designator Pin List] to keyword hierarchy. - RESOLVED 5. Remove [Number of EMD Pins] keyword? - CLOSED 6. Add definition of "Nyquist". - CLOSED IBIS-ISS Parser: - IBIS-ISS parser scope document