================================================================================ IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ================================================================================ Attendees from November 13, 2019 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff SiSoft Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* Michael Mirmak convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Michael called for review of the minutes from the October 23, 2019 meeting. Walter Katz moved to approve the minutes. Bob Ross seconded. The minutes were approved without objection. Review of ARs: - Walter to add the signal_name and bus_label capability to tie all the pins to a single terminal. - Walter reported this was done in draft 23. - Walter to add EMD bus_label by default rules to match BIRD182. - Walter reported this is done. - Walter to add merged pin example cases to the EMD BIRD. - Walter stated he added an example, but this needs reviewed. Arpad Muranyi asked if this was the same as Randy's previous AR. Michael commented Randy had two examples one with a stacked die and one with power rails added to that stacked die example, which was still being worked on. Walter stated his example shows the new syntax. Opens: - Bob noted one topic is if we want to support EBD through EMD. We need to close out this question. Arpad agreed that this was a question he raised that is still open. - Arpad asked about the email he sent and if those comments have been resolved. Walter replied he attempted to address those comments, but he would like the group to review them. EMD Status: Walter shared the latest draft 24 that he started. He added a paragraph, on page 15, for the bus_label rule when there is no bus_label or the bus_label is set to the signal_name. We add the designator interface for pin_name, signal_name, or bus_label. And, these have specific rules in the new paragraph. He changed the rules to be specific to the designator and EMD Pin List. We do not have the capability to support all pins with a rail signal_name. Michael asked if this closes the first two ARs. Walter stated the example is toward the end which shows the new syntax changes. He was not sure if this covered the merged pins case. Bob provided text which might replace some of what Walter had proposed. Bob limited rail pins into single pins and only this case would be supported. This is one difference between his proposed text and Walter's. If you want to group pins, you need to use singal_name or bus_label. The signal_name is all the pins, and bus_label is a way for the model maker to break up the pins in any way they want. There is no added rule about bus_label and signal_name being the same. Bob suggested to make it clear that we do not cross barriers across designators, as you don't want to accidentally create a short. Walter stated Bob wants to prevent shorting signal_names together. We could create a bus_label or make a list, but Bob's proposal would force bus_label to be used. Walter noted the other issue is if we can short two signal_names and Bob's proposal would prevent this. Arpad was concerned about long lists of pins and if this would cause line length limit issues. Walter stated you could use two lines, but we would have to add syntax for this. Bob stated we should not support a list, as this is a syntax variation. We should not cross designators terminal connections, where U1 and U2 would short to the same terminal of the EMD model. Bob noted that the long list of pins has to be cross referenced. Michael suggested to deffer discussing the issue until Randy can comment. He suggested to ask the issue over the reflector. Arpad was torn on the issue and had concern if the syntax can allow for all the merged pin cases. Bob stated one issue is the EMD board model maker has all the information, and the pins can be broken out with bus_labels to match the topology. One of the applications of the breakout is to split the core and IO VDDs. Arpad asked about the case if we have a board model with a power plane with one pin and only one VDD terminal is connected. Bob stated you would have to explicitly define the shorts, and if you want them to be open, they would be left unconnected. Arpad commented you may want the additional pins to be open so you don't short out the package rail model. Walter stated the issue is if you have a connection at the EMD level how to you connect the PDN of the EMD to the PDN of the designator. We need to have well defined rules on how to connect the PDNs. Bob stated it requires a separate designator model to connect the PDNs. We need to precisely define the the EMD pins. Walter requested for everyone to review draft 24 and focus on the following questions [AR]: Can we put multiple pin_names with the same signal_name on a single terminal? Can we put multiple pin_names with different signal_name on a single terminal? Can we put multiple signal_names on a single terminal? Walter to send out draft 24 [AR]. Michael asked if we should look at draft 23 or 24. Walter suggested to look at draft 24 since in contains the latest editorial changes. Next Meeting: The next meeting will be November 20. Walter moved to adjourn. Bob seconded. The meeting adjourned without objection. ================================================================================ Bin List: EMD Comments to be Resolved: IBIS-ISS Parser: - IBIS-ISS parser scope document