====================================================================== IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from November 16 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki, Ming Yan Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Michael Mirmak convened the meeting. No patents were declared. Review of Minutes: - Michael called for review of the minutes from the November 9 meeting. Walter moved to approve the minutes. Bob seconded. The minutes were approved without objection. Review of ARs: - Bob to check Examples 10 and 11 and resolve whether they are for IBIS-ISS or Touchstone. - Michael reported this is done. - Michael to summarize existing rules of precedence in the IBIS specification. - Michael reported he is still looking through the IBIS 6.1 specification to summarize these. Bob asked if he was looking for all the rules of precedence and not just those related to packaging. Michael replied that he is looking for all rules. Bob mentioned he gave a Summit presentation on overrides several years ago and that there are a lot of them. He is concerned that this could be a big task if we are to document all of them. Opens: - Bob sent out a revised table of terminal types that needs to be reviewed. Michael stated that we will try to get to it later on. Interconnect BIRD draft 43: Michael stated that draft 43 has been sent out, but he is not sure if it has been posted. Walter noted that there have been no changes from what he has sent out. Michael commented the phrase "die-pads" may need to be changed. Michael also noted that the pins, pads, and buffers connection question is discussed in this section on page 9. Walter stated that you have 3 cases of [Interconnect Model]s including: between pins and buffers, between pins and pads, or between pads and buffers. The introductory text does not give any constraints on the model connections. Bob pointed out that the [Interconnect Model Set]s are the encapsulation of one or more [Interconnect Model]s, with those three choices. Bob thought it might be better to list the three choices in bullet form in the document. Bob commented that terminals are used to enable the connections between these 3 groups. Walter mentioned that in this first section he did not want to introduce terminals yet, but terminals are introduced on page 10. Bob is concerned in the case where an [Interconnect Model Set] can contain only rails. Walter stated the compelling reason for this is that separate EDA tools could be used to create the rail models and signal models separately for each the die and the package. He suggested that if Bob wants to change the rule then he should make a motion to do so. Bob said that he would like to put it on the table to discuss that [Interconnect Model Set]s must contain a complete path from pin to buffer. Michael clarified that Bob wants to add a sentence that only complete paths can be included in an [Interconnect Model Set]. Michael mentioned he would like to see some examples, and asked if anyone has cases where this rule would cause a problem. He asked if you need the complete path for both I/O and supply rails or is it only a problem for I/O. Bob replied that an [Interconnect Model Set] that consists of buffer to pad does not define the full path and is a broken connection. Walter commented that IC vendors may have one silicon that goes into different packages as well as multiple silicon going into the same package. Randy confirmed that he has both of these cases. Walter stated that if you are allowed separate sets for the silicon and for the package, then you can easily combine these. If this is not allowed, then you would have to combine these combinations in different sets. In either case, the EDA tools still must make the connections. Arpad asked if it would be helpful to have independent [Interconnect Model Set Selector]s for each package and die. Walter said this should work with the current [Interconnect Model Set Selector], but it is up to the EDA tool and user to make the correct selections. Bob brought up a Micron example Randy had given a while back. The example consists of different silicon configurations used in the different packages. Randy mentioned that these use the same silicon die but are configured differently for x4, x8, and x16 DQs. Bob commented that this is a case where the buffer to pad interface is the same in all cases. In his approach, it is more convenient for the user to not have to search for models to match up or possibly selecting incorrect combinations of models. Randy asked if we have different sets that need to be combined, does the model maker need to carefully document which sets to connect together. Walter thought the EDA tool and user would select the sets through the selector. The EDA tool should produce an error or warning if you have missing connections. Michael asked if there is a simple way to look at the rule. And if anyone has any examples where it is necessary to break the rule. He solicited the group to provide examples to highlight the issue. Walter commented that the picture on page 10 is of a package substrate. Bob thought the picture is difficult to read and could use some labels. Walter noted that buffer terminals are not shown, and agreed we could use some better pictures. Michael mentioned he is still looking into it. Bob suggested that the table he sent out could be used as a guideline for the ordering of the text. Walter commented that this introductory text is justification for the table. Bob thought that we are getting to far into the details in the introduction. Walter agreed that the text could be rearranged, but asked if the text is accurate. Bob suggested for everyone to look at the Allowed Terminal_type Associations table order that he sent out. Michael suggested to not have a meeting next week on November 23 and resume the meeting in two weeks on November 30. The ordering of the table and the introductory text will be discussed. The main issue is the split model case. Walter commented we already have an example for his argument. Walter moved to adjourn. Bob seconded. The meeting adjourned without objection.