================================================================================ IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ================================================================================ Attendees from November 20, 2019 Meeting (* means attended at least using audio) ANSYS Curtis Clark Cadence Design Systems Bradley Brim Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki Mentor, A Siemens Business Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SiSoft Walter Katz*, Mike LaBonte Teraspeed Labs Bob Ross* Michael Mirmak convened the meeting. No patents were declared. Justin Butterfield took minutes. Review of Minutes: - Michael called for review of the minutes from the November 13, 2019 meeting. Randy Wolff moved to approve the minutes. Bob Ross seconded. The minutes were approved without objection. Review of ARs: - Everyone to review draft 24 and consider the following questions. "Can we put multiple pin_names with the same signal_name on a single terminal?" "Can we put multiple pin_names with different signal_name on a single terminal?" "Can we put multiple signal_names on a single terminal?" - Michael noted we will discuss these questions today. - Walter Katz to send out draft 24. - Michael reported this was done. Opens: - Michael asked Randy if he had an updated example. Randy stated he did not have any update to the example, although it would be good to update the example based on the new syntax. - Michael asked if the terminology list has been added with definitions for the terms "connected", "short", and "component". Walter noted we have changed component to designator and connected and short are used but this needs to be reviewed. EMD Draft 24 review: Walter stated the two non-editorial items are multiple pins and EBD in EMD. Michael asked if there were any changes to the draft based on the AR questions. Walter replied that there were not, as we need to make a decision on these. Michael asked Randy to comment on the three questions. Regarding: "Can we put multiple pin_names with the same signal_name on a single terminal?" Randy asked if the alternative is that you would use a bus_label. Walter replied if they are all the same signal_name this can work. If you have VDD and VDDQ and you want to short them at the EMD pins, they would be different signal. If the intention is to short the two rail voltages, this would be the mechanism to do that. Randy stated we need to be able to short two pins that have a different signal_name. We need a mechanism at the board level you would want to short the out for instance VSS and VSSQ. Randy asked how this would work with the [Designator Pin List]. Walter noted you can short them in the EMD model. Arpad Muranyi asked if you label one pin as VDD if this shorts the other VDD pins. Walter stated we do not allow two or more signal_names or bus_labels to be shorted together. Randy asked if this can be done in the syntax or needs to be done inside the model. If at the [Designator Pin List] you list everything with VSS, will that short the VSS and VSSQ? Bob noted it is not clear we are only talking about one interface, and there could be issues across the different designator interfaces. The terminals of those interfaces can get merged to one point. Walter asked if we want to allow two different designators to be shorted together. Bob replied we do not want different signal_names to be shorted. Walter suggested to have Randy take a detailed look at this and make sure we can support the needed functionality in the syntax. Arpad asked if the shorts are on the signal_name or bus_label, and if this will connect to that pin_name only or to all the pins. Walter replied it is up to the EDA tool what it connects to that one terminal. All the current will go through that one pin on the model. Arpad suggested to make this clear in the specification. Bob suggested there should not be auto shorting at the EMD side. Walter stated people will most often use signal_name to connect the terminals. He asked if we want to be able to short signal_names VSS and VSSQ on the EMD side and at the designator side. Bob noted this should be allowed at one interface only. He disagreed with shorting two signal_names. Randy stated he would be okay with this. If we have VSS and VSSQ with different signal_names at the EMD level, the signal_name can be VSS to short them, and the labeling should be matched at the hierarchy level. Walter asked about the paragraphs on page 28 and 29 which would allow shorts in several places. He asked if we are okay with removing this text. Bob stated he favors removing the auto short capability. Randy agreed with removing this text. Walter stated he will remove the paragraphs on page 28 and 29 and create a draft 25 [AR]. Randy suggested to close Arpad's question about which pins are connected on a signal_name. Walter added this as a comment to the draft. Walter stated we will need to think about this. Walter asked if there is any objection to removing the paragraphs. Bob noted we don't want implicit connections. Walter stated he will try to address this for next time. Randy agreed, if you only specify one pin, then the others should be left unconnected. Bob suggested to write this as a rule. Randy asked if we still allow a list of pin names at a terminal. Walter replied for any one terminal there will only be one pin_name and this will be true for I/O and rail pins. Walter noted, in the [EMD Designator Map], we can have .ibs and .emd. The question is if we want to allow .ebd in the EMD Designator Map. Randy stated if you support the EBD it can be convenient to support existing models. But, with EBD, there is no PDN model. Arpad commented, if you have an EBD with signals only, the connections could still flow correctly. He does not see any technical reasons to not allow EBDs. Walter commented you can supply power through the EMD, but there are no rail pin_names in the EBD. Randy noted the EDA tool would be forced to use the ideal power from the model in this case. Walter stated an EBD will prevent you from doing power delivery and differential models. Bob suggested to not allow EBD, as it has an implicit global ground. Walter stated it is trivial to write a conversion script to convert an EBD to EMD. Randy asked if this would convert the path descriptions to IBIS-ISS. Walter replied this is what is done in many tools now. Walter asked if there were any objections to not allowing EBD. There were no objections stated. Michael asked if all the questions have been addressed. Bob suggested we will need to review the draft. Walter stated he believes we have an understanding of the needed changes. Bob stated we still need to address the single pin for rail issue. Michael asked if we want to skip the meeting next week. Walter moved to not have a meeting next week. Bob seconded the motion. There were no objections. Next Meeting: The next meeting will be December 4. Randy moved to adjourn. Bob seconded. The meeting adjourned without objection. ================================================================================ Bin List: EMD Comments to be Resolved: IBIS-ISS Parser: - IBIS-ISS parser scope document