====================================================================== IBIS INTERCONNECT TASK GROUP http://www.ibis.org/interconnect_wip/ Mailing list: ibis-interconnect@freelists.org Archives at http://www.freelists.org/archive/ibis-interconn/ ====================================================================== Attendees from December 9 Meeting (* means attended at least using audio) ANSYS Curtis Clark* Cadence Design Systems Bradley Brim Cisco David Siadat Intel Corp. Michael Mirmak* Keysight Technologies Radek Biernacki* Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff* SAE ITC Maureen Lemankiewicz, Logen Johnson Signal Integrity Software Walter Katz*, Mike LaBonte* Teraspeed Labs Bob Ross* University of Aveiro in Portugal Wael Dghais Michael Mirmak convened the meeting. No patents were declared. Walter Katz moved to approve the minutes of the previous meeting. Arpad Muranyi seconded the motion. The minutes were approved without objection. Michael noted that the agenda included both Mike LaBonte’s review of his example drawings, and Walter’s discussion on probes in the document. Mike reviewed his example drawings. While showing Subckt 1, he noted that there is a general path from terminal 1 to terminal 12. He asked whether a 2-buffer drawing is the kind of circuit we would want to show, with separate signal pins but multiple power pins, in the specification. Walter responded, yes, absolutely. Radek Biernacki replied that using multiple power pins may be misleading. Randy Wolff added that we want to show multiple subcircuits – one for the package and one for the die. Walter noted that coupling is not shown in several places; for example, between signal pin A1 and signal pin A2. Walter also noted that the names of the pins should not be “POWER” but instead “VDD” – the intent is to use the signal name, not the model name. Michael asked whether the numbers used are instance nodes or subckt nodes. Mike replied that these are Terminal nodes, and are also the instance names. Michael stated that he opposed “overloading” of the terminology. Walter stated that the pad name is in the list of die supply pads. Signal_name corresponds to the signal_name section; pin_name corresponds to the first column under [Pin]. Bob Ross requested an example with two buffers instead of four. Mike stated that the paths shown in the diagram are just approximate. Arpad replied that they suggested to the readers that they think of them as wires. Walter suggested that only one or two drawings should be sufficient for the document, as they would be simple, small, and easy to handle. Mike showed a second document, combining pins and diagrams, which may form a cookbook-style document to be issued separately. Walter suggests this be an informative document to accompany the normative Interconnect BIRD. An IBIS wiki may be the best option, instead of a Cookbook. Mike will select two drawings for the Interconnect BIRD. Walter commented that, last week, the team established that no probes are desired for the document by anyone that he knows about. He sent out a message asking about probes, and received only one response, suggesting removal. Arpad added that probing is up to the EDA tool to attach the probe (it’s a node, it’s there, therefore the EDA tool can report aspects about it). Walter replied that probing here was intended to be between the pin and die pad. Michael asked whether the team was proposing prohibiting probes altogether, or just using the separate node terminal. Arpad suggested that the tool and user can always rename nodes for connection purposes. Walter moved to remove probes from the Interconnect text. Arpad seconded removing probes from Interconnect text. No objections were raised. The motion was approved. Michael will remove probes from the next draft (#27). Mike’s drawings will also be added. Bob noted that the question of die pads vs. bus labels is still to be discussed. Michael noted that the next meeting will convene on a normal schedule, but that end-of-year holidays may change the meeting schedule thereafter.