====================================================================== IBIS INTERCONNECT TASK GROUP MEETING http://www.eda.org/ibis/interconnect_wip/ Mailing list: ibis-interconn@freelists.org ====================================================================== Next meeting: Dec. 12, 2012 8 AM US Pacific Daylight Time Agenda: - Attendance - Call for Patents - Agenda and Opens - Brief Update on Discussions with Si2 and Related Planning - Die-to-die Needs and EMD - Next Meetings’ Schedule/Agenda: Dec. 19 and 2013 Meetings For international numbers, please contact Michael Mirmak. ......................................................................................................................................... Join online meeting https://meet.intel.com/michael.mirmak/QZ193W0C First online meeting? [!OC([1033])!] ......................................................................................................................................... <--- Reservationless Bridge – Do not edit or remove --- 916-356-2663, 8-356-2663, Bridge: 2, Passcode: 8625431 Speed dialer: inteldialer://2,8625431 -----------------------------------------------------------------> Note: in case of issues with Lync we will use the WebEx noted at the bottom of this message ====================================================================== Attendees, Dec. 5 Agilent Technologies Radek Biernacki ANSYS Luis Armenta*, Steve Pytel Cadence Design Systems Brad Brim* Intel Michael Mirmak* Mentor Graphics Arpad Muranyi* Micron Technology Justin Butterfield*, Randy Wolff Signal Integrity Software Walter Katz* Teraspeed Consulting Group Bob Ross* Minutes No patents were declared. No opens. Michael Mirmak explained the outcome of discussions with Sumit DasGupta of Si2. Their IP rules prohibit public disclosure of specifications in a “quiet period.” For the interconnect-relevant specification, this quiet period will end in mid- to late February. Specific details cannot be discussed until then. Bob Ross asked who is in Si2 and involved in their interconnect effort. Brad summarized the SI2 membership. Several members are also involved with IBIS. Walter noted that EMD ends at the die pad, not at the die. If the focus is on the silicon itself, Si2’s expected approach has an impact on the .ibs side of the system interconnect. Brad Brim suggested that If the document that Sigrity released for MCP existed as a standard today, the team would need to consider that in today’s EMD work. If EMD work proceeds, we would need to do so with the assumption that MCP is already in-use effectively as a standard. Arpad Muranyi reported that the ATM teleconference asked about analog modeling constructs needing to be resolved. Supporting files issues have been closed, backchannel/repeater BIRDs are in progress, dependency tables have been tabled because of a lack of decisions about analog modeling questions. An example is BIRD 116, making IBIS-ISS part of IBIS through External Model, A/D and D/A converters and the like. Walter suggested that buffer issues and interconnect issues are separate, and on-die interconnect should connecting the two. IC vendors are combining interconnect and buffer in a Touchstone file. Michael suggested that the only thing touching Interconnect’s responsibilities is the direct use of Touchstone files as buffer capacitance, as the file link approach should be similar to that used for passive interconnects. Walter Katz presented an overview of die-to-die connections in EMD, to address some aspects of interconnect modeling known to be of interest to Si2, based on previous presentations. He stated that EMD can be used to read and interact with the “footprints” in a PCB database, with reference designator, corporate part number, pin numbers, etc. The EDA tool uses all these to define electrical connectivity, with the EDA vendor supplying connectivity between PCB models and device models Brad replied that he agreed with this approach until last paragraph on page 8. If the EDA vendor is assumed to handle connectivity between devices and the PCB in a post-layout environment (all of the devices and boards are “modules”). Connectivity is external to the module. What about inside the module? Walter responded that they are hierarchical; the package might call an interposer which might call a stacked die; inside the module there’s a hierarchy of connections . Michael asked whether the models are nested/recursive down to .ibs and ISS primitives. Walter answered that this is true, everything is converted to netlists by the tool from the EMD. X,Y coordinates become a different handle for the pin number. Bob Ross asked a general question: what can the Si2 proposal do that the EMD proposal can’t do, and vice-versa? Specifics of the Si2 proposal could not be discussed. Walter suggested that the implication is that the subcircuits in Si2 may not be IBIS-ISS; may be some other language, but the approach is still a description of circuits inside of a box that has “bristles.” Michael asked about pre-layout. Walter suggested that the EDA tool takes care of PCB extraction and hooking up the models of the board – the tool has to select the pins (really, the user does this) of interest on the module. This assumes the EMD is supplied by IC vendor or package vendor. The tie-in is done by user. In post-layout, tool does it this automatically. You can make an EMD for the backplane, and an EMD for the daughtercard, and EMD for … and an EMD to hook them up. Then you don’t need a PCB separate model anymore. EDA tool takes care of connections. Michael asked about next steps. Walter stated that everything is taken care of outside of the specifics of MCP and Si2. If we describe everything in terms of pin numbers, everything is there in EMD (not a trivial process to fill in the details). If we talk about different ways to interface modules other than by pin number or pin name. The IBIS problem is how to tie ports to IBIS-ISS structures; then ISS can be used for interconnect between package pins and die pins. Si2 would come in for interconnect between die pads and buffers themselves. Package pins to die pads would be handled by IBIS as a specification. Brad suggested that what’s missing is passive interconnect at the device layer. Walter replied that S4Ps are being used for die pad return loss today.. Bob asked which one approach (Si2, EMD) will companies use? Walter answered that vendors will provide tools to tie the two together based on port definitions. The next meeting will review how buffers may be tied to interconnect, and BIRDs that are involved with or blocked by interconnect-related issues. This includes BIRDs 116, 117, 118, 122, and how package pins tie to die pads. Arpad asked that analog BIRDs and IBIS-BSS be included. ====================================================================== In case of Lync issues only, we will switch to WebEx as noted below. Meeting Number: 732 940 715 Meeting Password: IBIS ------------------------------------------------------- To join this meeting (Now from mobile devices!) ------------------------------------------------------- 1. Go to https://sisoft.webex.com/sisoft/j.php?J=732940715&PW=NNWY2NmRmZTY0 2. If requested, enter your name and email address. 3. If a password is required, enter the meeting password: IBIS 4. Click "Join". 5. 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