Integrated Microcomputer Division Folsom California Date: May 7, 1993 From: Donald Telian (916) 356-5029, fax -6710 Subject: Minutes from IBIS Open Forum 5/7/93 To: Attendees, list Attendees: Hyperlynx - Kellee Crisafulli Integrity Engineering - Greg Doyle Intel Corporation - Will Hobbs, Tim Schreyer, Gary Saunders, Arpad Muranyi, Donald Telian IntuSoft - Matthew Archambault Meta-Software - Stephen Fenstermaker, Mei-Ling Wei MicroSim - Arthur Wong Quad-Design - Jon Powell, Chris Myles Quantic Labs - Mike Ventham, Zhen Mu List: Intel - Randy Wilhelm Overall Summary: This document contains the minutes of the second IBIS Open Forum, held on May 7, 1993. The meeting was attended by all seven software simulation tool vendors who have announced support of IBIS modeling. The meeting was quite productive, in that we completed an in depth technical discussion of the remainder of the ASCII template that was not discussed on 4/23. This discussion focused primarily on the proper generation/documentation/usage of V/I curve data and ramp rates. Basic agreement was reached between all parties, a couple open issues identified (with owners) for next meeting, and a general consensus that we should be able to close on the "content" of IBIS ASCII version 1.0 at the next meeting on 5/21/93. Open Issues: Various issues were brought up during the meeting. I'll use this section to track those issues, and site when they'll most likely be addressed # | Description | Owner | On Agenda When? | Done 1 | New Keyword under pullup/pulldown | Powell | During V/I disc. on 5/7 | 5/7 2 | tri-state v/i curve | GD/JP | 5/21, Quad presents | 3 | Hierarchical model/file structures | Doyle | During V/I disc. on 5/7 | 5/7 4 | How is v/i and ramp data derived | Wong | During V/I disc. on 5/7 | 5/7 5 | if & when to pass IBIS 1.0 to stds committee | Doyle | 5/21 or 6/4 | 6 | golden parser, what is it? who owns it? | Powell | 5/21 | 7 | format of PKG file | Telian | 6/4 | 8 | thresholds for timing | Powell | 5/21, Doyle presents | 9 | buffer delay to ramp | Powell | please document | 10 | add examples with 1.0 release | Crisaful | Telian will do | 11 | ECL model extensions | GD/CM | ?????? | Minutes: I. Announcements: Telian announced: 1. "IBIS Capable" waveforms must be returned to Telian by 5/20/93 if you want to be on Intel's list of "IBIS Capable" simulation tool vendors. This list will be distributed in early June to the Intel sales force world-wide. Intel's Field Applications Engineers (FAEs) will use the list to recommend tool platforms to our customers. 2. Also, software simulation vendors need to deliver a date to Telian on when their platform will support the full library of 82430 PCIset models, already released in the Pentium (tm) Processor Open Design Guide in the IBIS format. 3. For the purpose of generating "IBIS Capable" waveforms, the following definitions hold for a "best" or "worst" case driver: best worst I_ol, I_oh max I_ol, I_oh min rise, fall min rise, fall max mins in pkg table max in pkg table 4. Some corrections in the "PCI_OUT" IBIS are: (1) currents in "Diode to GND" column should be negative (PCI_IN IBIS too), and (2) I_oh @ V_oh of 10V should be 55 mA min and 137 mA max. II. 4/23 Minutes review, Open time for new issues: MicroSim pointed out some inconsistencies between the 4/23 minutes and the ASCII template relating to the [Comment char] keyword and the [IBIS Ver] keyword. In all cases, now and in the future, the ASCII is upheld has accurate. The mistake was in the minutes. New issues were added from Quad Design ("buffer delay to ramp" as noted above), and Hyperlynx requested that we release example files of the ASCII template with 1.0. III. TEMPLATE.IBS, focus on V/I curves and ramp times: We had some general discussion on labeling data columns "fast", "typical", and "slow" to help clarify which parameters would be combined to make a "typical" model or a "fast" model. This was rejected by the group, in favor of just labeling values "min" or "max". In general, the tools will allow the end user to build up models from the raw data supplied in the ASCII. For example, the user could try the minimum V/I curve with the maximum or minimum package inductance, if desired. It was noted, however, that it would be a nice feature for the end user to simply pick a "fast" or "best-case" model, or a "slow" or "worst-case" model (and perhaps, even define what he wants that to be). V/I Discussion: 1. A new keyword [Voltage range] will be added to each [Model] description to specify both (1) the voltage range the modeling data was derived over, and (2) the end voltage tolerance the model is expected to be simulated at. This keyword will be followed by typ, min, and max values. 2. It was agreed to post the data as Vcc-relative, as written. All IBIS models should be adjustable to any voltage in the entire [Voltage range], and this manner of posting the data facilitates this. In general, voltages under [Pullup] and [Vcc_clamp] will represent the difference in voltage potential from Vcc. 3. Everyone agreed that the V/I curves will be derived according to the definitions for min, typ, and max on page 6 of the TEMPLATE.IBS faxed for the meeting. The posted data will then span voltage, temperature, and process, and it will be up to the simulation software to scale the values intelligently over the voltage range. It may also be possible for the tool vendor to do scaling for temperature or process, but this is not defined at present. The intention is to allow the simulation tool to get to reasonable best or worst case models, and not necessarily all intermediate points. 4. The voltage sweep covered by each V/I curve was approved as defined for 5V (page 6), but Intel will update the tables to show what the ranges would be for other component voltages. Tri-state and Input V/I Curves: There was some discussion about including optional tri-state and/or input V/I curves. Quad has an application that warrants a separate tri-state curve, and bipolar inputs (or other) could warrant an input V/I curve. Discussion was tabled until the 5/21 meeting. Hyperlynx noted that a simple thevenin voltage source and resistance would be adequate for the input model. ACTION ITEM: Quad Design. Write up a proposal explaining the need for more V/I curves, and explain how to incorporate into IBIS ASCII. An optimum proposal would address both tri-state and input curve data needs. Fax proposal to Telian or the entire group prior to 5/18 in order to discuss at 5/21 meeting. (Also, as a separate item, include a description of your desire for "buffer to ramp delay" data as raised under Open Issues). Ramp Rates: The ramp rate methodology was approved as documented in the fax, with the deletion of the parenthesis () around the data. The forward slash "/" between dv and dt values will stay to facilitate data entry and user friendliness, and the parsers will have to understand and discard it. Input and Switching Thresholds: It was decided to post the AC test voltage, V_test, and capacitance, C_test, along with Vinl and Vinh to specify the parameters the driver's AC specifications were tested to. In addition, there is interest in specifying other thresholds and measurement points, but this discussion was tabled until the 5/21 meeting. ACTION ITEM: Integrity Engineering. Write up a proposal explaining the need for extended thresholds and measurement points, and explain how to incorporate into IBIS ASCII. Fax proposal to Telian or the entire group prior to 5/18 in order to discuss at 5/21 meeting. IBIS Open Forum: Minutes of 5/7/93 Meeting, Page 1 IBIS Open Forum: Minutes of 5/7/93 Meeting, Page 1 IBIS Open Forum: Minutes of 4/23/93 Meeting, Page 2