DATE: 3/3/98 SUBJECT: 2/26/98 EUROPEAN IBIS SUMMIT Minutes VOTING MEMBERS AND 1998 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Norio Matsui, Raj Raghuram Cadence Design (& UniCAD) C. Kumar*, Don Telian, Patrick Riffault, Craig Lewis, Greg Fitzgerald, Paul Galloway*, Patrick Dos Santos*, Catherine Weiss*, Alain Tribaudot*, Cypress (Bruce Wenniger) Digital Equipment Corp. Jeff Chu, Greg Edlund, Bob Haller Hewlett Packard (EEsof, etc.) Karl Kachigan, Henry Wu, Paul Gregory High Design Technology Razvan Ene* HyperLynx Kellee Crisafulli, Matthew Flora Incases Olaf Rethmeier, Scott Jacobson, Werner Rissiek* Intel Corporation Stephen Peters, Arpad Muranyi, Frank Kern, Will Hobbs*, Prakash Radhakrishnan* Columbia, SC (formerly NCR) Dave Moxley Mentor Graphics (Zeelan, Bob Ross*, George Opsahl, Mark Noneman, Interconnectix, etc.) Tom Dagostino*, Karine Loudet*, Jean Oudinot*, Manuel De Almeida*, Stephane Rousseau* Mitsubishi (Hoang Nguyen), Tam Cao Motorola (Ron Werner) National Semiconductor Syed Huq*, Cheng-Yang Kao, John Goldie, Ikchang Song North East Systems Associates Edward Sayre, Kathy Breda (NESA) NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments Thomas Fisher, Harvey Stiegler, Vincent Chang, Jean-Claude Perrin*, Peter Forstner* Thomson-CSF Jean-Marc Claveau*, Laurent Duzaic*, Saverio Lerose*, Benoit Meyniel*, Jean Lefebvre* Viewlogic Jon Powell, Chris Rokusek, Guy de Burgh*, Gary Mandel* VeriBest Ian Dodd, David Weins*, Ian Gabbitas* VLSI Technology D.C. Sessions Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1998: Actel Eric Tardif*, Emmonvelle Gaudin* Aerospatiale Lionel Dreux*, Claude Huet* Alcatel (Bell, Espace, etc.) John Fitzpatrick*, W. Temmerman*, Laure Bessettes*, Jean-Claude Pourtau*, Daniel Peron* ALS Design Yves Mouquet* Ansoft Eric Bogatin Apple Fred Floresca, Danny Itani Apteq Design Systems Dan FitzPatrick CERN Olivier Clere*, Jean-Michel Sainson*, Rudi Zurbroken* Compaq Shariq Rahma EIA Patti Rusher EMC Fawn Engelmann ENST, Paris Jean-Jacques Charlot* European CAD Standardization Adam Morawiec* Intitiative (ECSI) Fairchild Semiconductor Peter LaFlamme H.A.S Electronics Haruny Said* Intracon Design Ltd. Derek Laidlaw* Philips Semiconductor Todd Andersen Scottish Electronics Robert Easson* Manufacturing Center (SEMC) Seagate Vanessa Howard SGS-Thomson Philippe Lefevre* Siemens Gerald Bannert*, Bernhard Unger*, Christian Marot*, Miguel Hernandez* Symmetry Andy Hughes Tektronix Nassrin Ghahyasi Ultratest International Chris O'Connor Xilinx Susan Wu In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode March 13, 1998 (916) 356-9200 5-23353 2913463 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM The European IBIS Summit was held in Paris, France at the Hotel Concorde La Fayette. Bob Ross welcomed the group and introduced the officers. All the attendees introduced themselves. During the meeting Bob thanked Mentor Graphics for sponsoring the excellent facilities and equipment, Cadence Design for the outstanding buffet lunch, and High Design Technology (HDT) for providing the refreshments. Bob also thanked Razvan Ene of HDT for initially suggesting an IBIS meeting associated with the Design Automation and Testing in Europe Conference (DATE98). This suggestion was developed into this European IBIS Summit Meeting. About 50 people from 20 organizations were recorded as attending. Please submit any corrections to organizations or names to Bob. (Also Bob thanks Karine Loudet for handling the local arrangements, signup, and providing copies of the presentations.) Some brief notes taken during the presentations from the presentation material are given below. The presentations themselves will be available on eda.org under /pub/ibis/summits/feb98. WELCOME, IBIS ACTIVITIES - Bob Ross, Interconnectix/Mentor Graphics, USA Bob gave a brief overview of the EIA IBIS Open Forum. The subgroup has open, public participation to all interested parties. He described the the technical evolution of the IBIS versions. The Open Forum monitors external, international activities such as the EMC and IBIS activities in France. The Open Forum also has several projects related to ratification of Version 3.1 including BIRD42.3 and the ibischk3 parser development (the first evaluation version has been distributed to those funding the project). It also cooperates with the IBIS Users Group (IBIS East). REPORT ON IBIS USERS FORUM - Paul Galloway, Cadence, USA Paul showed the mission and history of the IBIS Users Group headed by Ed Sayre. The Group has two committees, one concerned with Accuracy and Validation of IBIS, and the other concerned with Software Aspects. Paul emphasized that the participation is open and has members from all over the USA. However, the four face-to-face meetings to date have been held in the Northeast USA, with the last three hosted on site at companies. Paul concluded by stating that the group is focusing on the users needs, has strong East Coast EDA tool vendor participation, and is coordinating its activities with the EIA IBIS Open Forum. USE OF IBIS MODELS IN ALCATEL - John Fitzpatrick, Alcatel, France John has written a simplified IBIS parser in PERL and showed pages of his Netscape browser interface for his IBIS Management Suite. It was developed last year. John uses the IBIS Management Suite to manage buffer models. He would like to have the model verification process to be robust enough to not require simulation or measurement of the buffer. A graphical datasheet shows the added curves to get the real response, and it can be used to filter out superfluous data. John also illustrated a simplified model creation process when exact information is missing, but he stressed that this is not for novices. Then entered information can be used for design rules, and he illustrated this for crosstalk for several technologies. For ASICs, John relies on the short circuit current rather than the Iol current for driver strength classification. By contract Alcatel requires IBIS models for ASICs, but in reality models are not provided. The IBIS format does not support independent [Model]s for buffers, although EDA tools do provide such support. John sees the need for IBIS package models for ASICs which are not readily provided. John stated that ASIC timing is based on Cload, but the actual load is not capacitive. He would like an exact threshold value (Vt) instead of Vinl and Vinh. He also claimed that the IBIS Model was not suitable for ground bounce simulation. John showed some examples for buffer strength and timing. While stating that IBIS support is better, John concluded with several recommendations: component and buffers may need to be managed separately, better ASIC library support - at least in the Cookbook, more emphasis on timing analysis and less on SI, good graphical tool is needed, and more package only models. IBIS MODEL DEVELOPMENT AT NATIONAL SEMICONDUCTOR CORPORATION - Syed Huq, National Semiconductor, USA Syed introduced himself as Vice Chair. and also the Web Master of the EIA IBIS Open Forum. He has been active since 1994, and National has provided the largest number of IBIS models. In the last three years National has also hosted the IBIS Summit Meetings associated with DesignCon. Syed discussed the IBIS Intranet, an internal National web page used for information, tools, training and an internal users group. National develops IBIS models from Spice using the public s2ibis2 and also an internally developed ns2spice for NaSpice. Also National develops measurement based IBIS models. Syed listed the steps he uses to validate models: visual inspection, s2iplt verification, ibischk2 parser test, simulation with two simulators under a know load, and comparison of simulation data to bench or Spice simulation. IBIS model development is a milestone step in the National digital device release process. National currently develops IBIS Version 2.1 level models and will develop IBIS Version 3.1 models when the ibischk3 parser is made available. Syed noted that Logic, Memory, and Discrete models are now handled by Fairchild Semiconductor, which spun off from National. IBIS, MEASUREMENTS VS SPICE - Tom Dagostino, Zeelan/Mentor Graphics, USA Tom compared the plots of several IBIS Model V_low tables from some publicly available components extracted form s2ibis tools with actual measured data. While the components were selected randomly, Tom's general observation was that the measurements tended to correlate with the max columns. The plots also showed some s2ibis artifacts of double counting the power clamp and some known numerical current foldback on the ground clamp side. REQUIRED IBIS ENHANCEMENTS - Gerald Bannert, Siemens, Germany Gerald shared his experiences. Along with correct logical functioning under normal operating conditions (signal integrity, crosstalk, propagation delay), he was concerned with incorrect function and failure conditions (on/off of multiple power supplies, voltage over/undershoots at inputs and outputs, and maximum operating frequencies under load condition), and long term reliability (junction temperature, breakdown voltage, and maximum currents). Gerald listed the important parameters. The group not covered by IBIS included: monotony of rising and falling edges at inputs, minimum and maximum rise and fall times at inputs, ground bounce effects, bus hold circuitry at inputs, and switching on/off conditions of multiple power supplies. Input capacitance and clamping diodes are covered by IBIS. The load normalization of data sheet delay times is an interface problem between different libraries. Gerald illustrated several of these parameters. He also concluded that the most critical parameters are difficult to define, measure and model; modeling parameters should take into account future practical needs; and the vendor interface is very important. The vendor interface includes these considerations: valid IBIS revisions, optional parameters, interpretation of IBIS parameters, feedback of simulation results to I/O (re)designs, model and/or silicon changes, and model validity and guarantee. CHALLENGES IN USING IBIS IN HIGH FREQUENCY APPLICATIONS - Prakash Radhakrishnan, Intel, USA Prakash discussed the need for an improved IBIS package model to simulate simultaneous switching noises and associated delay interactions. He showed results using the existing discrete LRC package model and using the coupled matrix model in IBIS Version 2.1. Prakash's enhanced model used a "hybrid modeling technique" developed to capture lumped and transmission line effects. It involves modeling a plane as a two-dimensional inductance array with discrete capacitive coupling between planes. This process gives more detail for ground and power planes and helps to improve the correlation between simulated and measured results. EUROPEAN CAD STANDARDIZATION INITIATIVE (ECSI) - Adam Moraweic, ECSI, France Adam began the afternoon presentations by briefly describing the ECSI as an EDA vendor funded organization to promote educational workshops and information about standards affecting the European community. IBIS could be a candidate for such a workshop. IBIS MODELS AND EMC SIMULATION STANDARDIZATION STATUS Jean-Claude Perrin, Texas Instruments, France Jean-Claude, President of the working group gave the presentation in place of Christian Marot who arrived later. The working group is affiliated with Union Technique de L'Electricite (UTE) of France and is UTE/CEF93/GT5 EMC. It is affiliated IEC TC93 WG5 to work on electromagnetic compatibility of ICs. Its objective is to create a standard for EMC integrated circuit models. Jean-Claude defined aspects of the EMC problems: signal integrity, emissions (radiated fields by PCB conducted noises on lines) and immunity (to radiated fields to conducted noises on lines). From a questionnaire issued by the group, Jean-Claude listed the conclusions and directions. Immunity was not in any software, IBIS was well adapted to the general EMC problem, but needed some improvements. For emissions, IBIS would need the following elements: coupling between I/O and power supply, coupling with the logic core, coupling between I/O, and feedback coupling between I/O. For immunity, IBIS would need these elements: equivalent decoupling impedance, impedance of supply lines, internal noise generator, internal loops, and coupling between internal logic and I/O. Measurement methodologies would have to be defined for model validation and control. The plan is to create a task force at the IEC level to present a New Working Item Proposal for September, 1998. An international experts meeting is scheduled on February 27, 1998 to disucss details. FUTURE COMPONENT CHARACTERIZATION FOR EMI ANALYSIS - Werner Rissiek, Incases, Germany Werner indicated that Incases and Viewlogic are working with the University of Missouri-Rolla on EMC component characterization. Werner described the EMC problem as an additional consideration beyond signal integrity and thermal radiation. The EMC problem involves strong magnetic fields in the area of ICs, and packages act as antennas. There exist differential and common mode effects. The general 3-dimensional solution is too large for accurate numerical analysis and for solving in a timely manner. So the proposed approach is to partition the problem and apply an expert approach with simplifying assumptions. Werner listed some geometrical and electrical parameters of interest. He further tabulated a number of electrical parameters for voltage, currents, time and clock frequencies and classified them as analysis (as an input parameter) or evaluation (of results). Tables for buffer specific parameters and derived quantities for components and buffer classification were shown. Werner concluded that the EMI analysis required behavioral models like IBIS, additional classification parameters for an expert approach, and specific geometrical package information. This information could be put into an extended IBIS. Werner stated that he is willing to help in the IEC task group. IBIS MODELS FOR EMC AND HIGH-FREQUENCY DEVICES - Razvan Ene, High Design Technology, Italy Razvan presented an architecture and Spice-like syntax sample for handling SI problems. It has time-switching functions, pullup and pulldown functions and clamping functions. Spice polynomial functions are used. Razvan showed the definition of the functions and an extension for time-varying clamping. Its data is extracted using a TDR setup. Razvan showed the results for the AC74 from two manufacturers and presented a distributed diode-inductor model for the slow clamping effect. Razvan showed some measurement versus simulation correlations. Regarding EMC, Razvan showed a measurement setup at the semi-anechoical room at Lille University and showed a test case. Even for low frequency simulations the model needs to be valid at very high frequencies. With "dft" extraction (replacing the slope given in the IBIS model), he showed EMC modeling and measurement correlation up to 400 MHz. For IBIS, Razvan recommends a number of practices and additions: use all fields (min, typ, max), introduce a field for Cout spread, use waveform tables, and introduce supplementary fields for TDR measurement and dynamic output impedance and clamping. Razvan also supports forming a European IBIS group to disseminate IBIS and IBIS know-how and to provide a forum where producers and users can express their needs. SI-ANALYSIS WITH HSPICE BASED ON IBIS BEHAVIORAL MODELS - Bernhard Unger, Siemens, Germany Bernhard showed an IBIS model architecture for analysis that uses time- varying multipliers for the pulldown and pullup tables to describe the switching from one state to another. He conducted a number of tests to generate the multipliers based on one-waveform and two-waveform test loads. These loads were based on waveforms generated with R_fixture = 50 ohms and V_fixture terminated to GND or Vcc. Bernhard's results showed good correlation with the two-waveform case or when the test loads matched the simulation loads in the one-waveform case. Bernhard presented some results of actual signal integrity simulations and comparisons with measurement of a circuit involving an IBIS based HSPICE model including package, transmission line model using the HSPICE U-model from parameters extracted using a 2-D field solver, and a vendor supplied connector model. He showed excellent agreement with measurement when he adjusted the pullup table using scaling factor of 1.3. Bernhard concludes that IBIS models with two-waveform tables extracted under two different loading conditions give results valid for a wider range of loading conditions. IBIS Version 1.1 models are not sufficient. PROBLEMS IN V-T CURVE MODELING AND SIMULATION - C. Kumar, Cadence, USA Kumar indicated that the waveform algorithm processing algorithms were still ambiguous. One waveform analysis can be handled in a arbitrary number of ways. If multiple waveforms are given, then any of the sets of choices can give different simulation results. The waveform algorithms do not address the power and ground current distributions correctly. Kumar proposed according to BIRD42.3 that V/T and I/T tables given for the same V_fixture and R_fixture load could be used unambiguously to solve for the time varying multipliers for the pulldown and pullup tables. He proposed R_fixture = 50 and V_fixture = Vcc/2 to capture the independent pulldown and pullup switching characteristics. BIRD42.3 ALGORITHM CONSIDERATIONS - Bob Ross, Interconnectix/Mentor Graphics, USA Bob indicated that he and C. Kumar were co-authors of BIRD42.3 that is still pending. An IBIS Version 2.1 reference model was presented, consistent with the prior models for waveform table processing. The BIRD42.3 additions include corresponding an optional [Pullup Reference Current] table and/or an optional [Pulldown Reference Current] table. Bob showed a possible and general enhanced structure for adding the current information to the IBIS Version 2.1 model using Idelta and Vdelta sources. With the addition current tables, there are algorithm issues. The added information can be used to revise the fundamental coefficient extraction, as Kumar proposes, or it could be also for corrections to the IBIS model. Also if both the [Pullup Reference Current] and [Pulldown Reference Curent] tables are given, they contain redundant data which needs to be resolved by the simulator. Because both the one and two voltage waveform methodology is used by simulators, the algorithms for the proposed current extensions need to be considered in detail for any of the optional extension combinations. Bob presented a table showing possible algorithm approaches for coefficient calculation and possible correction source calculatons for the allowable one and two voltage waveform cases with and without currents. In some cases either the V1,V2 information or the V,I information could be used for calculating coefficients, and the additional data used to calculate the correction sources. Bob listed several other issues associated with BIRD42.3. The added current information most likely would be available only from Spice extraction. Numerical issues may exist concerning this data. Other Model_types related to Open_* and ECL_* configurations had to be considered. The optimal set of Fixture voltages could be contradictory (Vcc and 0 for V1 and V2 tables, Vcc/2 for V1, I1 tables). Finally internal components such as internal clocks could introduce current spikes that are not included in BIRD42.3 extensions. GROUP DISCUSSION Jean-Jacques Charlot introduced himself as a Professor at ENST, Paris and he is concerned about the need for IBIS education. Bob Ross indicated that this was a general concern. Bob asked if people felt that the meeting was worthwhile, and the general consensus was very positive. The meeting was adjourned so that people could engage in individual discussions and make contacts. NEXT MEETING: The next teleconference meeting is on Friday, March 13, 1998, 8:00 A.M. to 9:55 A.M. BIRD46.1 may be scheduled for a vote. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785 huq@rockie.nsc.com Staff Applications Engineer, National Semiconductor, M/S A-2595 2900 Semiconductor Drive, Santa Clara, CA 95052 SECRETARY: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic (formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for use at trade shows. ==============================================================================