DATE: 12/10/98 SUBJECT: 12/7/98 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 1998 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Norio Matsui, Raj Raghuram* Cadence Design (& UniCAD) C. Kumar, Don Telian, Patrick Riffault, Craig Lewis, Greg Fitzgerald, Paul Galloway, Patrick Dos Santos, Catherine Weiss, Alain Tribaudot, Geoffrey Ellis, Todd Westerhoff, Ken Willis, Mike LaBonte Cisco Systems Syed Huq*, Sergio Camerlo, Irfan Elahi Compaq Shariq Rahma, Jeff Chu, Bob Haller, (Digital Equipment Corp.) Doug Burns, Steve Coe Cypress Bruce Wenniger* H.A.S. Electronics Haruny Said Hewlett Packard (EEsof, etc.) Karl Kachigan, Henry Wu, Paul Gregory, Brenda Arena, Hans Wiggers* High Design Technology Razvan Ene HyperLynx Kellee Crisafulli, Matthew Flora, Gene Garat, Dave Kohlmeier Incases Olaf Rethmeier, Scott Jacobson, Werner Rissiek Intel Corporation Stephen Peters, Arpad Muranyi, Frank Kern, (& formerly NCR) Will Hobbs, Prakash Radhakrishnan, Mohammed Hawana, Martin Chang, Dave Moxley, Tim Schreyer, Lyndell Asbenson LSI Logic (Symbios Logic) Larry Barnes Mentor Graphics (Zeelan, Bob Ross*, George Opsahl, Mark Noneman, Interconnectix, etc.) Tom Dagostino*, Karine Loudet, Jean Oudinot, Manuel De Almeida, Stephane Rousseau, Neven Orhanovic, Mohamed Mahmoud, Kevin Cohan Mitsubishi Tam Cao Motorola (Ron Werner) National Semiconductor Cheng-Yang Kao, John Goldie, Ikchang Song, Milt Schwartz* North East Systems Associates Edward Sayre, Kathy Breda, Michael Baxter, (NESA) Jon Green, Jinhua Chen NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments Thomas Fisher, Harvey Stiegler, Vincent Chang, Jean-Claude Perrin, Peter Forstner Thomson-CSF Jean-Marc Claveau, Laurent Duzaic, Saverio Lerose, Benoit Meyniel, Jean Lefebvre Viewlogic Jon Powell, Chris Rokusek*, Guy de Burgh, Gary Mandel VeriBest Ian Dodd, David Weins, Ian Gabbitas VLSI Technology D.C. Sessions*, Derwin Mattos* Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1998: 3Com Steve Miller 3Dfx Interactive Ken Wu A.T.Sinker Tony Sinker Actel Eric Tardif, Emmonvelle Gaudin Aerospatiale Lionel Dreux, Claude Huet Alcatel (Bell, Espace, etc.) John Fitzpatrick, W. Temmerman, Laure Bessettes, Jean-Claude Pourtau, Daniel Peron ALS Design Yves Mouquet Ansoft Eric Bogatin Apple Fred Floresca, Danny Itani Apteq Design Systems Dan FitzPatrick Atmel Ali Baktashian Avanti Nik Bannov CERN Olivier Clere, Jean-Michel Sainson, Rudi Zurbroken Corning John Nieznanski Crucial Technology Rathna Reddy DIVA Corp Tieng Nguyen Dynamic Research Corporation Mike Walsh EIA Patti Rusher EMC Fawn Engelmann, Fabrizio Zanella ENST, Paris Jean-Jacques Charlot European CAD Standardization Adam Morawiec Intitiative (ECSI) Fairchild Semiconductor Peter LaFlamme Focus Technology John Salzillo, Gary Brophy, Mike Arieta, Jim Skane Hyundai Farhad Tabrizi* IBM Richard Steinle, Kevin Jackson, Greg Edlund, Douglas Stout* InRange Elliot Lipin Intracon Design Ltd. Derek Laidlaw LG Semicon America Michael Spooer*, Seung-Tae Lee* Micron Technology Terry Lee* Molex Gus Panella Philips Semiconductor Todd Andersen Rockwell Semiconductor Tim Gilbert Scottish Electronics Robert Easson Manufacturing Center (SEMC) Seagate Vanessa Howard Signal Integrity Software Barry Katz SGS-Thomson Philippe Lefevre Siemens Gerald Bannert, Bernhard Unger, Christian Marot, Miguel Hernandez, Gil Russell, Hartmud Terletzki* SSEI Tom Hawkins Stratus Bruce Heilbrunn, Steve Mango, Lewis Steiner, Karla Eignor, Rich Newell Summit Computer Systems Bob Davis Sun Microsystems Lam Dong, Kevin Ko, Tay Ansari, Ken Weiss, Derek Tsai* Symmetry Andy Hughes Tektronix Nassrin Ghahyasi, Tom Brinkoetter, Brad Weber, John Rettig Teradyne Michael Khusid Time Domain Analysis Systems Dima Smolyansky Transmeta Bill Gervasi* TranSwitch Bill Todd TRILOGIC Joe Socha Ultratest International Chris O'Connor Xilinx Susan Wu, Rob Eccles* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode December 18, 1998 (916) 356-9200 3-241993 1195347 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ----------------------------------- IBIS SUMMIT MEETING The IBIS Summit Meeting was held at the Shelter Pointe Hotel and Marina in San Diego, California at the same time as the JEDEC JC-40 and JC-16 meetings. About 19 people representing 16 organizations participated in the meeting. The food, refreshments, and the facilities were excellent. The Minutes here just briefly note some of the content of the meeting and some discussion. Some of the presentations and related documents will be uploaded at: http://www.eda.org/pub/ibis/summits/dec98 INTRODUCTIONS AND BUSINESS - Bob Ross (Mentor Graphics) After a delicious buffet lunch for attendees, Bob Ross opened the IBIS meeting by having the participants introduce themselves. There appeared to be equal representation from the IBIS and JEDEC communities. The semiconductor sector was more heavily represented than the user and EDA tool vendor sectors. An underlying theme of this meeting was to introduce and discuss possible new modeling requirements and needs. Following this theme, the EIAJ activity on I/O Interface Model for Integrated Circuits (IMIC) would be discussed because it had some possible ideas to deal with details that might not be currently handled well in IBIS. Bob noted that due to the last minute introduction of BIRD57 on Timed Bus Hold Extension, we are deferring the vote on IBIS Version 3.2 that had been scheduled for Friday, December 18, 1998 to the following meeting scheduled on Friday, January 15, 1999. That will give us time to review in the December 18, 1998 meeting the pending BIRD56 and BIRD57, initiate possible ibischk3 changes, and prepare IBIS Version 3.2 for voting with these BIRDs included. Bob also summarized that the next IBIS Summit Meeting is scheduled on Monday, February 1, 1998 at DesignCon99 in San Jose. The EIA IBIS Open Forum is an Associate Sponsor of DesignCon99 allowing DesignCon99 to provide the meeting facilities and refreshments. National Semiconductor will sponsor the luncheon. In the past, National had sponsored the whole meeting including facilities. Milt Schwartz will be the contact person for signing up meeting participants and signing up and gathering presentations. A first notice should be issued this week. The focus of that meeting will be on Accuracy issues and future IBIS features. Also, through the Associate Sponsorship arrangement, there will be an IBIS booth on the Exhibition floor that will provide IBIS information and demonstrate the IBIS User's Group accuracy test board measurements. Jon Powell is the contact person for the booth. Ad Hoc presentations and discussion topics were solicited: Active Terminations - Derek Tsai Bus Switches Functionality - Tom Dagostino Accuracy Testing of Measurement Based Models - Tom Dagostino JEDEC JC-16.2 IBIS Presentation - Bob Ross PROGRAM NOTES FOLLOW (Scheduled and Ad Hoc Presentations): INPUT THRESHOLD MODELING - D.C. Sessions (VLSI Logic) D.C. Sessions noted that as a result of tighter timing margins, the old input threshold limits such as Vinh = 2.0 V and Vinl = 0.8 V are becoming too conservative to be practical. Input signals can easily have a ledge in the in the region between Vinh and Vinl. The actual thresholds are much tighter. Also JEDEC JC-16.2 is standardizing on closer threshold limits for newer technologies. D.C. noted that for many technologies, the Input thresholds were related to the power supply voltage. So D.C. suggested a linear adjustment factor that is related to the rail to determine more accurate thresholds. Bob Ross mentioned that this might already exist indirectly using the [Model Spec] keyword. D.C. also noted that the timing delay was a function of how much the input signal went over the first threshold. D.C. showed some time shifted responses as a function of threshold overvoltage from 25 mV to about 1.6 V. The delays shrank from about 3 ns to 300 ps. For this particular simulation, D.C. fit the data to a 2/3rds power relationship: t = to + K/(Vin - Vth)**(2/3) D.C. suggested a timing table could be proposed for IBIS to capture this input resolution. To summarize, D.C. presented the following draft proposal: 1) Threshold Voltage "Add a first-order term to the exiting Vin specs. DC trip point is defined as the specified value at the specified supply voltage plus (the new value) times the difference in supply voltage. Alternately, add a table. In effect, turn the current and scaler values into lists." 2) Timing "In keeping with IBIS's preferred use of observable properties, add an [input_delay] table giving relative delay for input voltages relative to the specified thresholds. Thus, if Vinl is 800 mV under some condition, the table entry at 200 mV is the added delay for signals at 1000 mV. Simulator providers would be free to innovate with respect to dynamic algorithms for complex input waveforms. OVERVIEW OF JEDEC JC-16 ACTIVITIES - Hans Wiggers (Hewlett-Packard and Chair. of JC-16) Hans Wiggers introduced himself as Chair of the JC-16 group under which there are two subgroups. The group is involved with interface topologies. They also provide an educational function. Hans commented that the threshold and input characteristics are of interest. Also a driver specification consisting of a Max and Min IBIS style table for bounding values is a current proposal under discussion for memory devices. Hans listed a number of standards that the group has been involved with. Low Performance standards include: TTL, LVTTL, LVCMOS, 2.5 V non-terminated CMOS, 1.5 V interfaces. High performance standards include: GTL, Center Tap Terminated, (High Speed Transmission Logic) HSTL -1, -2, -3, -4, (Series Stub Terminated Line) STTL for 3.3 V, now 2.5 V and future 1.5 V. The best inputs are with a terminator to Vtt = Vddq/2 (the quiescent Vdd voltage). Hans showed some network topologies to illustrate this. One distinction is that JEDEC standardizes parameters that can be put in data sheets. Data sheet information is contractual; customers can reject the components if they do not meet the data sheet specifications. So there is a reluctance for very tight parameters which may be hard to test against. The immediate future activities of JEDEC JC-16 are modifying STTL-2, adding IBIS-like tables to driver specifications, and specifying LVCMOS for 1.5 V. ACTIVE TERMINATIONS (Ad Hoc) - Derek Tsai (Sun Microsystems) Derek Tsai showed a device/net topology with a switchable termination and asked whether IBIS Version 3.1 could cover it. The topology involved a pullup termination Rup that was active only in the driving mode. Rup and Rdn source and load terminations were equal to Zo and were switchable from up to down states. It appeared that Rup was disabled only in the receiver mode. Derek listed some characteristics: 1. Back-to-back switching 2. Rup acts as termination (active) and never turns off until it needs to drive "low" 3. Rdn drive '0' 4. Fall: Rup -> Rdn Rdn -> Rup and stays on 5. Problems: 1) transition has glitches, 2) bus contention (under work-around simulations) There was some discussion and clarification. Bob Ross indicated that pending IBIS Version 3.2 had submodel parameters both for dynamic clamps and for bus hold style circuits. While Bob thought that the bus hold extensions documented in pending IBIS Version 3.2 would model Derek's circuit, discussions during a break revealed that perhaps the dynamic clamp in the static mode was the appropriate representation. SERIES SWITCH EXTENSION (Ad Hoc) - Tom Dagostino (Mentor Graphics) Tom Dagostino drew a topology showing nets containing series switches that were turned on and off to control the connection paths. Tom asked if the turning on and off characteristics of the on/off and off/on transitions of the switch itself were important to model. Several people responded that they needed to model such effects. The series switch extension in IBIS Version 3.1 models only the static on or static off impedances in the path itself, but not the transition characteristics. IMIC DISCUSSION - Bob Ross (Mentor Graphics) Bob Ross introduced the background of why we are discussing the IMIC activity at this meeting. Bob indicated that the IBIS Committee people had been following the IMIC activity since February, 1997 through October, 1998 as a result of several private meetings and several IBIS Summit presentations on IMIC. At the London IEC meeting in September, 1998, the request was made that the IBIS committee work with the I/O Modeling Project group responsible for IMIC since the activities appeared to overlap. Bob indicated that there were subsequent meetings with Dr. Hideki Fukuda in October, 1998 on this subject and that the topic was appropriate at this meeting since it related to potential IBIS future extensions. As an introduction, the IMIC activity had begun in 1996 to extend IBIS Version 2.1. The intent was to create extensions to deal with signal integrity, power integrity (ground and power bounce and SSO simulations), and EMI simulations. Also, the extension was needed to deal with emerging buffer topologies. Bob noted that IBIS also expanded its capability leading to IBIS Version 3.X extensions. However, there could be limitations to the IBIS behavioral approach that could be solved by IMIC and SPICE approaches. Bob summarized the IMIC approach both in his presentation and copies of slides provided by Fukuda-san. IMIC formats Modules (similar to IBIS EBD), ICs (Similar to IBIS Components and Models), and Packages (similar to IBIS Packages). However, IMIC supports a SPICE netlist syntax plus some IBIS wrapper keywords. IMIC also introduces a table SPICE representation of MOSFET, Diode and Bipolar devices that allows process information to remain proprietary. The models can be complex as shown by 1D (corresponding to IBIS, 2D and 3D samples. However, there could be efficiencies associated with scaling the buffers rather than providing different models for each physical geometry variation. Bob noted that IMIC does not include some specification and informational details contained in the IBIS format that are used by many simulators used for digital circuit board design and analysis. Such information includes model type (e.g., Input, Output, I/O, etc.), threshold specifications, timing test loads, and some connection information documenting differential I/O pin connections, power rail pin connections, etc. Bob outlined some IBIS/IMIC approaches: Merge IBIS and IMIC Link from IBIS to IMIC features of interest Keep IBIS and IMIC separate, but provide IMIC to IBIS translation paths There are practical and business advantages and disadvantages to each of these approaches. The most interesting is to explore Linkage to the package extensions and to the buffer formulations. These also relate to possible SPICE linkages and to both Table Spice and BSIM Version 3.2.2 extensions being standardized by the Compact Modeling Council. Bob noted one novel feature of the IMIC format is that it might be possible to format typical, minimum and maximum package characteristics in the same document. Bob was interested in accuracy validation of the table SPICE approach, and this is a subject in the next presentation. An IBIS committee study group consists of Stephen Peters, Raj Raghuram, Norio Matsui, and Bob Ross. Others are welcome to join. The EIAJ group will also have a small group for interaction. In the subsequent discussion, Syed Huq pointed out the IMIC is not an officially approved standard - it is still in draft mode and has not gone through official acceptance processes. In contrast, IBIS is an approved ANSI/EIA standard. VALIDATION OF EIAJ IMIC MODELS - Raj Raghuram (Applied Simulation Technology) Raj Raghuram also presented an overview of IMIC using selected copies of older presentations. The multi-dimension table format is an extension of Berkeley SPICE. The approach is supported by several commercial SPICE simulators, and the tables can be automatically generated by 3D DC sweeps and selecting the options to print capacitances at each point. With generic SPICE, more analysis work is needed by doing AC analysis at each operation point to extract capacitances. The validation process was to generate a Table SPICE model from a driver SPICE model, and then compare the simulation results of each under the same set of test loads. Example 1 used the Motorola 74LCX245 low voltage CMOS Octal transceiver model as the basis. Simulations were done with these driving parameters: 1 ns Tr, 1 ns delay, 9 ns pulse width. The results were compared with these test circuit loads: 500 ohms and 5 pF to ground, 50 ohms to ground, 50 ohms to Vcc (3 V), and 500 ohms terminating a 50 ohm and 1 ns transmission line. All of the results showed very similar waveform shapes when overlayed. There was a slight delay mismatch, but Raj considered that a problem based on low Table SPICE resolution. He did not have time to investigate and provide refinements to this skew in results or to investigate the effects of 3D to 2D model simplifications. Example 2 compared a Texas Instruments CBT16233 with a Table SPICE formulation. The device was loaded with a 1 kiloohm and 5 pF at the end of a 65 ohm and 1 nS transmission line. Excellent, overlaying response was shown between the orignal SPICE model simulation and table SPICE models generated from Applied Simulation Technology and HSPICE simulators. Raj concluded that the correlation was good and that the IMIc model is a viable SPICE-like alternative that protects proprietary process information. ACCURACY TESTING OF MEASUREMENT BASED MODELS - Tom Dagostino (Mentor Graphics) Tom Dagostino raised the question and led the discussion on what is needed to test the accuracy of measurement based models. A number of points were made relating to accuracy and to what should be included in a measurement based model are captured here. One point is that measurement based models document actual characteristics of the device. However, since it was not known whether that device was really typical, the scaling of the device data for min and max characteristics should be left to the simulator tool. It should not be given in the model. D.C. Sessions was interested in a range for different processes. Tom indicated that measurements could be done on a number of devices from the same vendor for different lots over time to get a statistical spread. Milt Schwartz and others indicated that sometimes the fabrication lab does not have the process skew information. Furthermore, there is a reluctance to provide too tight of information which will result in being forced to guarantee tighter information in the data sheet. So the documentation of lots was becoming less rigorous. Tom asked if it were valid to test different devices from a same technology from the same vendor, and several people stated that this was not valid since even with what is documented as the same family, the actual devices may have different characteristics and come from different processes or die sizes. So it was not a defendable practice to infer that different characteristics were related to min and max variations. Regarding test and extraction conditions, Chris Rokusek and other people stressed that capturing the information based on the IBIS Cookbook conditions of 50 ohms to ground and to Vcc and testing against those conditions was a preferred approach. There might be some exceptions, but even if the voltage swing is not full scale, the model was still tuned to the actual transmission line connections that need to be simulated. Other test loads could be included in the IBIS model for the purposes of validating the model, although few people are doing this. Examples of a validation load are connection of 50 ohms to Vcc/2 and using some capacitive loads. D.C. Sessions commented that he expected that the contributions of process variation, temperature variations (over a 0 degrees C to 125 degrees C) and a 10 percent voltage variation to have about equal contribution effects. So if IBIS models are extracted from measurements under simultaneous voltage and temperature variations, it might be defendable to infer the process variation effect by some additional scaling by 1/2. Chris indicated classified accurate models as Level 0: ramp based Level 1: one waveform based (one rising, one falling) Level 2: two waveform based (two rising, two falling) Chris felt that the Level 0 and Level 1 models were of comparable accuracy, and Level 2 models provide a great improvement. D.C. pointed out that the two waveform extraction provided both the turn on and turn off characteristics needed for the complete characterization. Chis noted that the 50 ohm load provided a better load line for actual operating conditions. D.C. mentioned that the 50 ohm extraction took into account the buffer Miller capacitance that affects the response. IBIS PRESENTATION AT THE JEDEC JC-16 MEETING (Ad Hoc) - Bob Ross (Mentor Graphics) Bob Ross indicated that Stephen Peters had been scheduled to do a presentation both at the IBIS Summit Meeting and also at the JEDEC JC-16 meeting, but he was unable to attend. So we needed to draft a presentation for the next day JEDEC meeting. D.C. Sessions provided some general guidelines, and the action was to work out presentation details at a dinner gathering with those people who would attend the JEDEC meeting. (Bob Ross and Chris Rokusek created a mostly hand-drawn IBIS Overview and Simulation presentation for the JEDEC Meeting on Tuesday, December 8, 1998. Several other IBIS committee participants attended. The presentation appeared to be well-received and prompted several questions. As an action item D.C. Session was asked to chair a JEDEC JC- 42 and JC-16 Task Group on Formation of IBIS Models. Initially people from Hewlett-Packard, IBM, Xilinx, Western Digital, United Memories, Micron, and Samsung joined this Task Group. Participation is also open to IBIS Committee participants. Contact D.C. Sessions to join.) NEXT MEETING: The next teleconference meeting will be on Friday, December 18, 1998 from 8:00 AM to 10:00 AM. BIRD56 and BIRD57 are scheduled for votes. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 SECRETARY: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 17641 NE 67th Court Redmond, WA 98052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic (formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================