DATE: 2/10/99 SUBJECT: 2/1/99 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 1999 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Raj Raghuram*, Norio Matsui* Cadence Design Mike LaBonte Cisco Systems Syed Huq* Compaq Bob Haller*, Steve Coe*, Shafir Rahman*, Maher Elasad* Cypress (Rajesh Manapat) H.A.S. Electronics (Haruny Said) Hewlett Packard (EEsof, etc.) Paul Gregory*, Henry Wu* High Design Technology (Razvan Ene) HyperLynx Matthew Flora*, Kellee Crisafulli* Incases Olaf Rethmeier Intel Corporation Stephen Peters*, Arpad Muranyi*, Frank Kern, Martin Chang, Dave Moxley, Kerry Nelson, Jeff Day, Richard Mellitz*, Peter Liou* LSI Logic (Symbios Logic) Scott King* Mentor Graphics Bob Ross*, Mohamed Mahmoud* Mitsubishi (Tam Cao) Motorola (Ron Werner) National Semiconductor Milt Schwartz* North East Systems Associates Edward Sayre*, Michael Baxter*, Kathy Breda* NEC (Hiroshi Matsumoto) Quantic EMC (Mike Ventham) Texas Instruments (Jean-Claude Perrin), Shankar Balasubramaniah*, Ramzi Ammar* Thomson-CSF (Jean Lebrun) Viewlogic Chris Rokusek, Guy de Burgh*, (Jon Powell) VeriBest Ian Dodd* VLSI Technology D.C. Sessions* Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1999: 3Dfx Interactive Ken Wu* Actel Corporation Silvia Montoya* Applied Microelectronics Brian Sanderson* Avanti Nik Bannov* Bogatin Enterprise Eric Bogatin* EIA Patti Rusher EMC Corporation Fabrizio Zanella* IBM Greg Edlund*, Michael Cohen, Praven Patel* Fairchild Semiconductor Peter LaFlamme*, Craig Klem* FCI John Ellis* Litton Systems Robert Bremer* Molex Incorporated Gus Panella* Rockwell Collins Susan Tweeton*, Ron Hau* Samsung Jung-Gun Byun*, Cheol-Seung Choi* Siemens AG Bernhard Unger* Signals & Systems Engineering Tom Hawkins* SiQual Scott McMorrow* StorageTek Nick Krull* Sun Microsystems Victor Chang* Teradyne Mikhail Khusid* Time Domain Analysis Systems Dima Smolyansky Xilinx Susan Wu* (Unaffiliatied, Retired) Bruce Wenniger* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode February 19, 1999 (916) 356-9200 4-2245000 7252452 Tuesday, March 9, 1999 IBIS Summit Meeting - No Teleconference All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ----------------------------------- IBIS SUMMIT MEETING The IBIS Summit Meeting was held at the Santa Clara Convention Center in Santa Clara, California. About 52 people representing 35 organizations participated in the meeting. These minutes just briefly note some of the meeting's content and some of its discussions. Most of the presentations and related documents are available on the World Wide Web at: http://www.eda.org/pub/ibis/summits/feb99 INTRODUCTIONS AND BUSINESS - Bob Ross (Mentor Graphics) Bob Ross opened the IBIS meeting by introducing the officers and then having having the participants introduce themselves. Bob thanked Milt Schwartz of National Semiconductor for handling the local arrangements and copying of presentations, and thanked National Semiconductor for hosting the buffet luncheon. Bob also thanked Jon Powell for arranging the booth and company logo placards (some of which were picked up at the meeting). Bob thanked the Accuracy Committee for providing the demo at the booth. Finally Bob thanked the DesignCon99 organization for providing the meeting room, the refreshments, the IBIS meeting room sign, the DesignCon99 booth, and publicity (a full page advertisement) in the DesignCon99 brochure. The EIA IBIS Open Forum is an associate sponsor of DesignCon99. Later Bob surveyed the participants and found that the semiconductor, EDA, and user sectors were all well represented. OPENS FOR NEW ISSUES Bob Ross called for Ad Hoc presentations and discussion topics. The following topics were added and covered during the meeting: Kellee Crisafulli - Flight Time Calculations in IBIS Simulations (Covered by Stephen Peters) Kellee Crisafulli - Who Supports the EBD Format? IBIS USER'S GROUP TELECONFERENCE MEETING Bob Ross indicated that there was interest by the IBIS User's Group in holding regular teleconference meetings on weeks that the IBIS Open Forum does not hold meetings. Bob indicated that Mentor Graphics is willing to provide a bridge for such meetings. [A meeting has been set up for Friday, February 26, 1999. More details will be announced later.] PROGRAM NOTES FOLLOW (Scheduled and Ad Hoc Presentations): OVERVIEW, REVIEW OF SUMMIT AGENDA - Bob Ross, Mentor Graphics Bob Ross started the main meeting by giving a brief overview of what has occurred during the last year. IBIS Version 3.2 was ratified and will be forwarded for ANSI/EIA-656A ratification. The ibischk3.2 parser is nearly completed, but still needs some refinements. IBIS Version 2.1 is moving forward, but still pending ratification as IEC 62014-1. Bob noted that over 350 people are on the IBIS reflectors. There are 26 member companies and over 70 organizations and over 170 people participated in IBIS meetings in 1998. Five face-to-face Summits were held. Bob also noted that he knew of over 30 different companies which provide web sites where IBIS models can be requested or downloaded. Other companies provide IBIS models directly. Bob stated that the meeting presentations cover Accuracy and Validation, a review of IBIS Version 3.2 features, and then move on to topics for potential future IBIS extensions. These include future requirements, a timing extension, IMIC discussion, and the connector modeling proposal. Bob concluded by mentioning his 5 C's for model Validation: Correct, Compliant, Complete, Checked, and Compared. Checked covers the syntax check, graphical viewing, visual inspection, and loading the model into a simulator. Later Greg Edlund suggested using Correlated as discussed in the Accuracy Specification rather than Compared . IBIS USER'S GROUP STATUS Ed Sayre, North East Systems Associates (NESA) Ed Sayre briefly reviewed the history of the User's group and sited two accomplishments of the IBIS User's Group: The Accuracy Specification and the Connector Model Specification. Ed stated that a 1999 goal was to produce an IBIS tutorial. He was willing to head the effort, but asked for volunteers to assist in preparing the material. Ed envisioned downloadable lesson blocks on IBIS and on how to use IBIS models. A number of items were discussed. Kellee Crisafulli mentioned that there should be no host preference. All EDA vendors could be represented in the material. Milt Schwartz stated that there should also be some basic material such as what typical I/O plots should look like. Susan Tweeton stated that how to produce ASIC models needed to be covered. Ed and D.C. Sessions noted that students in Universities get no exposure to IBIS. Kellee noted that a typical student project costs about $18,000 per student. THE IBIS ACCURACY SPECIFICATION: STATUS AND DIRECTION - Greg Edlund, IBM Greg Edlund supplied Revision 1.1 of a Draft Accuracy Specification and also an IBIS Accuracy Trailer draft. In the presentation Greg noted that Correlation was the cornerstone of the IBIS Accuracy Specification. Greg defined a figure of merit relationship for an overlay metric between laboratory measurements and simulation. The Specification should be a reference document for purchasing semiconductor parts. It is not a pass-fail standard for judging accuracy. It needs to be user driven and flexible. The current status of the document is to support Version 1.1 IBIS features. A test board has been developed, and its design along with other documents are uploaded on the http://www.eda.org/pub/ibis/accuracy site. Revision 1.2 of the Specification will fold in V/T tables. The goal is to pursue EIA approval of Revision 1.2. Greg thanked the contributors to the document and outlined the contents. He discussed the proposed test structures and then showed examples of the envelope and correlation metrics. Four correlation levels are proposed in the document, but only three will be proposed in the future version based on the availability of the component sample. The proposed levels are 1: Random, 2: Known Typical, and 3: Known Typical, Fast and Slow. In response to comments that the correlation needs to factor out possible simulator differences, a judiciously chosen golden waveform will be proposed. It might be based on a SPICE reference simulation of the SPICE model from which the IBIS model was derived. Such a golden waveform might require an IBIS extension to include the test load structure. This led to a number of questions and discussions. The golden waveform was further discussed by Ed Sayre, Stephen Peters and Paul Gregory. It could be a correlation reference for EDA tools. Scott King mentioned that in doing ASIC models, the package information was introduced separately based on the ASIC package. Scott McMorrow cited the importance of the package information in current devices, yet indicated that it is difficult to extract. D.C. Sessions cautioned against sneaking in benchmarks. Stephen stated that the model documentation could be used as a confidence factor. Susan Tweeton cautioned that the model documentation should not be mis-used as an excuse to pitch the EDA tool. In response to the criticism that the specification will raise the model cost and cause too much work, Greg noted that too many simulation failures will create the crisis that forces semiconductor vendors to document their correlations. Greg concluded by asking for more volunteers. A bi-monthly teleconference call will be initiated. The correlation section will be revised. The group will propose a BIRD to support Golden Waveforms. The plan is to forward the updated document for EIA approval. Also, more research is needed for test loads to cover enhancements beyond IBIS Version 1.1 functionality. PRACTICAL USE OF IBIS MODELS AND ACCURACY STUDIES - Fabrizio Zanella, EMC Corporation Fabrizio Zanella presented some results comparing measurements with simulations using IBIS models and also comparing SPICE model and IBIS model simulations. Fabrizio stated the advantages of using IBIS models for board level simulation: The board file can be imported directly without recreating the topology, and IBIS models are easy to use, fast and accurate for board level simulations. Fabrizio showed some correlation results. One important result was to show equivalent ring back. Several comments were made regarding the bandwidth of of the test equipment and probe parasitics and whether the device was really typical to explain some differences. Fabrizio felt that for off-board analysis, SPICE simulation was a better option, especially for high speed clock nets, since connector models are available and lossy lines can be handled. He showed some measurements and SPICE simulation correlation. In addition, Fabrizio showed some correlation of a TTL test case with IBIS simulation using SPICE, and direct SPICE model simulation. There were some differences with overshoot and pulse widths. Some of this was discussed and questions were raised. For example, one SPICE simulation indicated that perhaps a clamping diode was not in the SPICE buffer model. The pulses did not overlay because the IBIS model may have chosen a different starting reference for rising and falling edges. Even so, Fabrizio concluded that IBIS model simulation did yield accurate results compared to laboratory data and produced similar results to SPICE simulations. FLIGHT TIME CALCULATIONS IN IBIS SIMULATIONS (Ad Hoc Presentation) - Stephen Peters, Intel Corporation Stephen Peters prepared some hand-drawn foils in response to the new agenda item. Stephen defined flight time as a way to account for the change in a device's propagation delay due to changes in device loading. He illustrated this by showing that the maximum clock period was calculated as the summation of propagation delay, net delay and setup time: Tpd + Tdelay + Tsetup. The timing test load (such as 500 ohms and 50 pF) along with Vmeas was used as a reference to extract the internal delay information, and its loading effect needed to be factored out for actual timing simulations. VALIDATION OF IBIS BASED TWO WAVEFORM MODELS - Bernhard Unger, Siemens AG Bernhard Unger presented some results of a study on two-waveform based IBIS models generated using 18 ohms, 50 ohms and 100 ohms as the fixture loads. The 18 ohm fixture was selected to produce about one-half the Vcc swing. Bernhard conducted the test using the Fairchild CMOS driver VCX16244 HSPICE model supplied by Peter LaFlamme as a reference and from which the IBIS model (also supplied by Peter LaFlamme) was generated. Four driver conditions were tested: (1) a 50 ohm, 1 ns transmission line loaded with 5 pF, (2) a lumped 500 ohm parallel 30 pF load, (3) a distributed 66 ohm transmission line load, (4) and a DIMM module 66 ohm transmission line load. The simulations were conducted with and without the Vdd/Vss package model parasitics. The simulations were done using two-waveform extracted Kpur(t), Kpdr(t), Kpuf(t) and Kpdf(t) table multipliers according to the SPICE implemented algorithm cited in previous presentations. Bernhard showed a number of overlaying comparisons and concluded that the 50 ohm fixture load provided a good compromise. The 18 ohm fixture load provided better correlation for the DIMM module test case since the effective impedance seen by the buffer was about 25 ohms. When the Vdd/Vss package effects were included, the results were not as well correlated. Bernhard concluded with the following points: (1) Two waveform behavioral model simulations provide excellent agreement with transistor based simulations if the IBIS V/T-table loading conditions are comparable with the simulation conditions and the Vdd/Vss parasitics are of minor influence. (2) 50 ohm V/T-table loading conditions seem to be a good compromise for most purposes. (3) IBIS models with different R_fixture loadings are a real need if timing and noise are very critical issues. (4) Vdd/Vss package parasitics strongly influence the simulation results with increasing transition times. As present, this feedback is not included in the IBIS model. Furthermore, Bernhard raised these questions: (1) Is there a set of IBIS V/T-table loading R_fixture loading conditions (four or five) that cover the range of application loading conditions for a given device? (2) What method determines the IBIS V/T-table R_fixture loading conditions to give the best fit with simulation loading conditions? (3) What are the possibilities to implement feedback caused by the Vdd/Vss package parasitics into IBIS behavioral models? D.C. Sessions commented that the load selection and results may be impacted by internal Miller capacitance in the output stage. LUNCH BREAK A delicious buffet luncheon was hosted by National Semiconductor. IBIS VERSION 3.2 OVERVIEW - Stephen Peters, Intel Stephen Peters gave an overview of the IBIS Version 3.2 extensions beyond IBIS Version 2.1. Version 3.2 was ratified by the IBIS Open Forum at the January, 1999 teleconference meeting and will be forwarded for ANSI/EIA-656A ratification. The golden parser is uploaded (it still needs some fixes). As background, Stephen stated that IBIS Version 2.1 supported I/V tables and V/T tables. It provided initially for GTL plus technology. However, it was limited in describing passive elements, it did not provide adequate multi-stage I/O buffer models and cartridge packaging technology, and lumped L/R/C package models were a practical limitation. Stephen gave an overview and elaborated (showing related keywords) upon four areas of IBIS Version 3.2 enhancements: (1) Support for additional device types - passive (2-pin) devices, terminators, bus switches (2) Extended model specs and simulation hooks - ringback and hysteresis specs, model selectors (3) Support for advanced driver/receiver technology - multi-staged outputs, bus hold, dynamic clamps (4) Enhanced package descriptions - transmission line package stubs, .ebd files. Stephen noted that the future enhancements include uncoupled and coupled connector models. The [Add Submodel] concept can be a path for future expansion since a submodel can be used for anything. There is consideration of a possible merger or incorporation of the IMIC specification. Kellee Crisafulli raised the question at this time regarding which EDA vendors support the .ebd format. Several vendors replied that several do provide support or will very shortly. IBIS FUTURES - Stephen Peters, Intel Stephen Peters continued the discussion by noting what IBIS does well. It handles CMOS/TTL/ECL technology and controlled rise time parts such as GTL. Bus hold is now available. The EBD and enhanced packages allow more complex paths - as long as coupling is not required. However, what is lacking is multiple buffer switching effects taking into account SSO effects due to pin to pin coupling and power/ground rail bounce. A lossy transmission line is needed. Perhaps it is time for the G matrix and/or a frequency dependent loss for .ebd and .pkg files. Non-ideal ground return paths need to be modeled in the next generation of simulators. Ed Sayre stated that impedance of the ground plane is a big problem, subject to possible university work. Stephen continued that the solution to these are important because of very fast processor buses and source synchronous signaling. The timing budgets are tight and the second order effects are now dominant. [Pin Mapping] is a start, but not complete. Pin to pin coupling is almost there, but needs improvement. A number of participants discussed aspects of physical databases, SPICE models and SSO effects. Stephen concluded that the key to SSO modeling is to make the buffer power and ground nodes available. IMIC is interesting, but does not use the standard I/V and V/T description of the buffer. Stephen also noted that the [Add Submodel] keyword has expansion possibilities for a model consisting of a group of buffers and for embedding package descriptions. VALIDATION OF EIAJ IMIC MODELS - Raj Raghuram, Applied Simulation Technology Raj Raghuram gave the first presentation of a two part presentation on IMIC. Raj introduced IMIC by noting that it was targeted for signal integrity, power integrity and EMI analysis. Such analysis requires the device model, the signal trace model and the ground/power plane model. The inner core of the IMIC model is a multi-dimensional table format as an extension to Berkeley Spice. Such tables can be generated by Spice2IMIC convertors. IBIS models can be generated from IMIC models. Raj described the validation process for both the Motorola 74LCX245 buffer and the Texas Instruments 74CBT16233 switch. Raj substituted the derived IMIC model tables for the process models. All the results showed nearly overlaying correlation with the original SPICE models. Raj also gave some details on making IMIC models. Several SPICEs support DC sweeps for printing three-dimensional Voltage/Current and Voltage/ Capacitance table information. RD, RS, and RSH should be set to zero. If a more generic SPICE is used, an AC analysis is needed at each point to extract the capacitances. Stephen Peters questioned how fast the IMIC model performs. Raj estimated that it was about twice as fast as SPICE, but such an estimate may be impacted by the table resolution. Scott McMorrow suggested a simplified and reduced IMIC model. Arpad Muranyi raised the concern that even though the process information is protected by using the table transistor model, the structural information, which also can be proprietary, is revealed. REPORT ON EIAJ IMIC STANDARD - Norio Matsui, Applied Simulation Technology Norio Matsui continued the IMIC presentation. He added that the Hitachi ALVCH16244 was also used for validation studies. Norio elaborated that work was being done for advanced package models for up to 2000 pin BGAs, QFP and CSP configurations. Package and Module descriptions need the free network descriptions for coupling effects, forks and loops, and frequency dependency. Norio noted that the I/O Model Project Group is currently working on the EMI Model Standard. Return current paths and are considered along with ground plane effects. Local ground planes reduce EMI. Some of the details in the presentation were not covered due to time limitations. However, Norio noted that one EDA vendor supports the IMIC format, and another is expected to follow. A new EIAJ subcommittee will be formed to consider EMI/EMC modeling for non-ICs and system level applications. Norio positioned the IBIS and IMIC committee activities and also considered the relative strengths and weaknesses of each format. Norio concluded that he would like to see a merger of activities through a subset approach: IMIC into IBIS or IBIS into IMIC. The EIAJ I/O Modeling Project Group has formed a subgroup to investigate IBIS and IMIC merger. The formal standardization process of IMIC is currently being postponed. INPUT THRESHOLD MODELING - D.C. Sessions (VLSI Technology) Note, this description is adapted from the description given for a similar presentation given at the December 7, 1998 IBIS Summit Meeting. D.C. Sessions noted that as a result of tighter timing margins, the old input threshold limits such as Vinh = 2.0 V and Vinl = 0.8 V are becoming too conservative to be practical. Input signals can easily have a ledge in the region between Vinh and Vinl. The actual thresholds are much tighter. Also JEDEC JC-16.2 is standardizing on closer threshold limits for newer technologies. D.C. noted that for many technologies, the Input thresholds were related to the power supply voltage. So D.C. suggested a linear adjustment factor that is related to the rail to determine more accurate thresholds. D.C. also noted that the timing delay was a function of how much the input signal went over the first threshold. D.C. showed some time shifted responses as a function of threshold overvoltage from 25 mV to about 1.6 V. The delays shrank from about 3 ns to 300 ps. For this particular simulation, D.C. fit the data to a 2/3rds power relationship: t = to + K/(Vin - Vth)**(2/3) D.C. suggested a timing table could be proposed for IBIS to capture this input resolution. D.C. provided formats at the meeting for such a timing table using the keywords [Rising Delay] and [Falling Delay]. The adjustments to the delay would be made relative to the specification thresholds. The 0 V value has 0 seconds of adjustments. These tables contain typ, min, and max columns. To summarize, D.C. presented the following draft proposal: 1) Threshold Voltage "Add a first-order term to the existing Vin specs. DC trip point is defined as the specified value at the specified supply voltage plus (the new value) times the difference in supply voltage. Alternately, add a table. In effect, turn the current and scaler values into lists." 2) Timing "In keeping with IBIS's preferred use of observable properties, add an [input_delay] table giving relative delay for input voltages relative to the specified thresholds. Thus, if Vinl is 800 mV under some condition, the table entry at 200 mV is the added delay for signals at 1000 mV. Simulator providers would be free to innovate with respect to dynamic algorithms for complex input waveforms. Some discussion occurred. Arpad Muranyi stated that an equation might be considered instead of tables. Scott McMorrow thought more tables might be needed for multiple edge rates. IBIS CONNECTOR MODEL STATUS - Kellee Crisafulli, HyperLynx Kellee Crisafulli along with Gus Panella gave a presentation. Kellee supplied CDs containing the presentation, the draft documents, and many examples of implementation. The presentation and other documents are planned to be uploaded. Kellee introduced the topic by naming the simulator vendors, connector vendors and end users who had participated in the development of the proposed specification. He presented the motivation related to what is missing in IBIS. This includes not having a method for modeling cascaded or tee methods for coupled matrices. Also, the current method does not allow for a "swath" simplification method. Currently the concepts are determined, and the specification, examples, and slide presentation are created. The CD contains this information and more. Kellee noted that the familiar keywords of the IC and .pkg specification are used for header information and defining types of matrices. The Connector Specification is intended to be a stand-alone specification. It will include pictures (JPEG), Stub matrices, Cascaded matrices, a swath matrix, and a Diagonal_matrix type. Changes include pin naming methods for connectors, the .ibiscnn file name extension naming convention, and relaxed line width restrictions. In response to potential questions, Kellee stated that the stand-alone document will be smaller and contain only the keywords needed for the connector models. The new Diagonal_matrix reduces the number of lines for the single line, uncoupled models versus a Banded_matrix of Bandwidth 0. Kellee and Gus showed some samples of the Connector Matrix syntax. Matrix sections are named. The Swath was defined as a small matrix used to define a much larger matrix. The syntax allows for defining how to terminate some end columns when the swath is used. For the left-hand and right-hand columns, the Swath matrix overlaps by a designated number of columns, and these overlap columns are terminated in a designated impedance. Other examples of matrix construction were presented for Stub matrices, and for the construction of the complete connector model. The short term goal is to transfer the Specification to the IBIS archive and solicit feedback from the IBIS Open Forum. The goal is to adopt the .ibiscnn as a revision to IBIS. The longer term goal is to create a parser for syntax checking. Also the accuracy of the .ibiscnn model needs to be checked by comparing it with SPICE simulations. Features may be added to the swath method. Lossy models need to be added along with support for .ebd capabilities. Unbalanced and balanced style SPICE connector models were shown. The comparison should be against the balanced type model for reflections, delay, crosstalk and risetime degradation. Kellee concluded by thanking Gus Panella for his time and the other participants, EMC for the phone bridge, and HyperLynx for the specification enhancements and CD-ROMs. Many points were discussed during and after the presentation. Arpad Muranyi suggested using a Conductance Matrix for losses. The method of Swath overlap was clarified. The reason is to approximate the edge effects. How to handle the reference ground was discussed. Some preferred no reference ground. Stephen Peters asked about pad capacitances and frequency limits. After some discussion Stephen concluded that it is reasonable for EDA tools to handle the pad capacitances from the physical design. The pin boundary would stop at the board surface. One new aspect is that unmated models would be supported. Two unmated models do not produce a mated model. Raj Raghuram questioned whether the matrices are Maxwell. He pointed out that the diagonal matrix is not Maxwell. The response was that the matrices for coupled sections are Maxwell. Uncoupled matrices are referenced implicitly to the global ground. The main action item is for the IBIS committee to review the proposal and provide feedback. CONCLUSION Bob Ross concluded the meeting by noting that the next teleconference meeting was scheduled for Friday, February 19, 1999. The Tekronix IPA 510 software proposal would be discussed. Also, the following meeting would be an IBIS Summit Meeting in Munich, Germany on March 9, 1999 along with the DATE99 conference. Bob again thanked the participants and presenters for contributions. NEXT MEETING: The next teleconference meeting will be on Friday, February 19, 1999 from 8:00 AM to 10:00 AM. The Tektronix IPA 510 proposal will be discussed and voted upon. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentorg.com Modeling Engineer, Interconnectix BU of Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, Oregon 97124-5961 SECRETARY: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 17641 NE 67th Court Redmond, WA 98052 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic (formerly Quad Design) 1385 Del Norte Rd., Camarillo, CA 93010 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================