DATE: 6/29/99 SUBJECT: 6/21/99 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 1999 PARTICIPANTS LIST: AMP (Martin Freedman) Applied Simulation Technology Raj Raghuram, Norio Matsui*, Neven Orhanovic Avanti Nikolai Bannov Cadence Design Mike LaBonte* Cisco Systems Syed Huq* Compaq Bob Haller*, Steve Coe, Shafir Rahman, Maher Elasad Cypress (Rajesh Manapat) EMC Corporation Fabrizio Zanella Fairchild Semiconductor [Peter LaFlamme], Craig Klem H.A.S. Electronics (Haruny Said) Hewlett Packard (EEsof, etc.) Paul Gregory, Henry Wu High Design Technology Razvan Ene HyperLynx (& Pads Software) Matthew Flora, Kellee Crisafulli, Lynne Green* IBM Greg Edlund, Michael Cohen*, Praven Patel Incases Olaf Rethmeier, Werner Rissiek, David Eagles, Wilhelm Arnoldi, Ulrich Losch Intel Corporation Stephen Peters*, Arpad Muranyi*, Frank Kern, Martin Chang, Dave Moxley, Kerry Nelson, Jeff Day, Richard Mellitz, Peter Liou, Will Hobbs*, Henri Maramis* LSI Logic (Symbios Logic) Scott King* Mentor Graphics Bob Ross*, Mohamed Mahmoud, Sherif Hammad, Jean Oudinot, Markku Kukkanen, Martin Groeber, Karine Loudet, Hisham Gamal*, Evgeny Wasserman* Mitsubishi (Tam Cao) Motorola (Ron Werner) National Semiconductor Milt Schwartz* North East Systems Associates Edward Sayre, Michael Baxter, Kathy Breda NEC (Hiroshi Matsumoto) Philips Semiconductor Todd Andersen, Peter Christiaans Quantic EMC (Mike Ventham) Siemens Bernhard Unger, Christian Mitschke, Manfred Maurer, Peter Kaiser, Wolfram Meyer, Gerald Bannert, Harmut Ibowski, Katja Zuleeg, Hans Pichlmaier, Eckhard Lenski, Kortheuer Udo, Christian Sporrer SiQual Scott McMorrow Texas Instruments Jean-Claude Perrin, Shankar Balasubramaniah, Ramzi Ammar, Thomas Fisher* Thomson-CSF (Jean Lebrun) Time Domain Analysis Systems Dima Smolyansky Viewlogic Systems Chris Rokusek*, Guy de Burgh*, Cary Mandel, (Jon Powell) VeriBest Ian Dodd* VLSI Technology D.C. Sessions* Zuken-Redac (John Berrie) OTHER PARTICIPANTS IN 1999: 3Dfx Interactive Ken Wu Actel Corporation Silvia Montoya Alcatel Steven Criel Analytical Edge Robert Easson Applied Microelectronics Brian Sanderson BMW Friedrich Haslinger Bogatin Enterprise Eric Bogatin Bosch Telecom Detlef Wolf ECI Telecom Daniel Adar EIA [Patti Rusher], Cecilia Fleming*, Dan Heinemeier Electronique Catherine Gross EFM Consulting Ekkehard Miersch FCI John Ellis Hitachi ULSI Hideki Fukuda* Infineon Thomas Latzel* Intracon Design Mike Osmond Litton Systems Robert Bremer Matsushita Atsuji Itoh* Molex Incorporated Gus Panella Nortel Networks Martin Hall (& at Viewlogic), Calvin Trowell* Oce Printing Systems Ernst Deiringer Praegitzer Design Rick Newell Rockwell Collins Susan Tweeton, Ron Hau Samsung Jung-Gun Byun, Cheol-Seung Choi Shindengen Tsuyoshi Horigome* Signals & Systems Engineering Tom Hawkins STMicroelectronics Fabrice Boissieres, Philippe LeFevre StorageTek Nick Krull Sun Microsystems Victor Chang, Kevin Ko* Tektronix Tom Brinkoetter Teradyne Mikhail Khusid VDOL Robert Novosel Xilinx Susan Wu (Unaffiliated, Retired) Bruce Wenniger In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode July 23, 1999 (916) 356-9200 8-27037 9387986 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- IBIS SUMMIT MEETING The IBIS Summit Meeting was held at the Hilton Riverside Hotel in New Orleans, Louisiana, near the site of the Design Automation conference (DAC99). About 27 people representing 21 organizations participated. (14 member companies participated). The minutes just briefly note some meeting content and some other business and discussions. Most of the presentations will be uploaded on the World Wide Web at: http://www.eda.org/pub/ibis/summits/jun99/ Bob asked presentors who have not done so to send him electronic copies. PRELIMINARY BUSINESS: INTRODUCTIONS Bob Ross opened the meeting by introducing Cecilia Fleming of the EIA and thanking her for handling the meeting's logistical and food arrangements. Bob noted that EIA has a booth at DAC which includes an IBIS poster created by Alpert Designs. Bob also thanked Matthew Flora for handling the meeting registration. Bob introduced the current officers in attendance (Bob Ross, Chair, Stephen Peters, Vice Chair, and unofficially Syed Huq, Webmaster), and also noted the services of Matthew Flora, Secretary and Jon Powell, Librarian who could not attend. Bob also welcomed several new participants from Japan: Hideki Fukuda, Atsuji Itoh, and Tsuyoshi Horigome. Everybody then introduced themselves. PRESS AND WEB PAGE UPDATES Bob Ross reported on several IBIS related articles. In the June 1999 issue of Printed Circuit Design, Keith Felton and Todd Westerhoff wrote a guest editorial article "High-Speed PCB Simulation, Is It Time for a Change?" on pp. 42-45 & 63. In the May 27, 1999 issue of EDN, the article by Dan Strassberg "Digital Busses, Analog Problems" pp. 73-86 gives brief mention of IBIS. In the June 7, 1999 issue of EE Times, Ed Sayre authored "Board Design Toes Transmission Line", pp. 70 & 84 and provides general IBIS information. "Signal Integrity and Behavioral Models of Digital Devices" by I.A. Maio, I.S. Stievano, and F.G. Ganavero, Proceedings of the 1999 Zurich Symposium on EMC, February 1999 investigates IBIS simulation algorithms. DEADLINE FOR SP-4557 Bob Ross noted that the deadline for ballots was June 23, 1999. Signed ballots needed to be returned to EIA by surface mail or by FAX. Cecilia Fleming noted that a strong show of support is needed. So far about 12 Yes votes had been received. Two contained some non-controversial comments. Later in the meeting Bob discussed the two comments: One comment suggested having Vmeas and Vref, Rref, and Cref mandatory for output and I/O buffers. The initial rationale for making them optional was to support upward compatibility from Version 1.1 level IBIS models which did not support these subparameters. The second comment was to implement the already approved BIRD58.3 editorial changes to IBIS Version 3.2. Bob suggested that a small group of officers review these and other comments that will come in and draft the formal responses for the IBIS Open Forum to review and approve. The ANSI deadline is August 3, 1999. Bob expected comments received by EIA after June 23, 1999 will still be considered. OVERVIEW PRESENTATION: IBIS 1998 - 1999 & MEETING OVERVIEW - Bob Ross, Mentor Graphics Bob Ross gave a brief summary of 1998 - 1999 progress. This included an update on the standards. IBIS Version 3.2 was ratified January 15, 1999 and is currently undergoing EIA and ANSI review as noted above. Also, IBIS Version 2.1 is going to enter the next phase (FDIS). The only objection to this was really a vote supporting IBIS Version 3.2 instead. Cecilia Fleming mentioned that IBIS Version 3.2 may be put on a fast track after the US ratification activity is completed. Bob provided the current statistics for 1999 participation and membership showing that the high level of IBIS activity has been maintained. Bob noted that besides the formal ratification issues, the major areas of concern are: IBIS Version 4.X additions, Connector Specification, s2ibis3 upgrade planning, IBIS User Group activities regarding the Accuracy Specification and Educational program, and Relationships with EIAJ IMIC and ECALS-2. The committee is following European EMC/EMI and JEDEC activity. On education, Bob noted that material from Arpad Muranyi and Todd Westerhoff could help seed the activity and has been uploaded to: http://www.eda.org/pub/ibis/training/ The remainder of the meeting was outlined as Business (Annual Election of Officers, etc.) Updates (Accuracy and s2ibis2/3 Committees) New Ideas (Behavioral Inputs and Equations) EIAJ Activities (IMIC and ECALS-2) IBIS Version 4.X Features Discussions Other Discussions and Ad Hoc Presentations (We ran out of time for the IBIS Version 4.X features discussion.) BUSINESS CONTINUED: ELECTION OF OFFICERS After some discussion, we added the position of Webmaster (to manage the Web content). D.C. Sessions suggested that Postmaster (to manage the mailing lists) also be added. The following people were nominated and unanimously elected to serve for the 1999 - 2000 year: Chair: Bob Ross, Mentor Graphics Vice-chair: Stephen Peters, Intel Secretary: Guy de Burgh, Viewlogic Librarian: Jon Powell, Viewlogic Webmaster: Syed Huq, Cisco Systems Postmaster: Matthew Flora, HyperLynx The motion was made to amend the bylaws and create the Webmaster and Postmaster positions and corresponding job descriptions. This was approved by a unanimous vote. Will Hobbs asked what is needed for a quorum and what vote is needed. Bob stated that he uses 5 as a quorum for teleconference meetings as stated in the original bylaws. However, Cecilia Fleming noted that we need to align our bylaws with EIA EP-20 for certain official votes. A majority of the official members are required for some votes, and a two-thirds majority is required for standards votes. Bob and Cecilia will research this. AR - Bob Ross and Cecilia Fleming research what is needed to align the IBIS bylaws with EP-20. AR - Bob Ross and Cecilia write position definitions for the new positions of Webmaster and Postmaster. APPRECIATION PLAQUES Cecilia Fleming and Will Hobbs (former Chair. of the EIA IBIS Open Forum) provided EIA plaques to the following people who served as officers (official and unofficial) in appreciation for their service during the last year: Bob Ross Stephen Peters Matthew Flora Jon Powell Syed Huq OPENS FOR NEW ISSUES D.C. Sessions - JEDEC JC-42.3 Report (discussed next) Tsuyoshi Horigome - Unscheduled presentation on Shidengen's Activity on EDA Model and Simulation of Electric Circuit (added at the end of the meeting) JEDEC JC-42.3 REPORT D.C. Sessions who serves in a (mutual) liaison roll between the IBIS Open Forum and JEDEC JC-42 reported on a recent Vancouver JEDEC JC-42.3 meeting concerning Double Data Rate SDRAMs. The JEDEC committee concluded that there is a characterization issue: the slew rate of 1V/ns depends on the loading conditions. The JC-42.3 Committee requests a specification (from the IBIS Open Forum) on derating the slew rate. The reason is that the current derating method works in test conditions, but not in real designs. PRESENTATIONS: (These notes just summarize some of the contents and some discussions on the presentations. Refer to the uploaded presentations for more content.) IBIS ACCURACY SPECIFICATION DAC UPDATE - Bob Haller, Compaq Bob Haller commented on some recent updates to the Accuracy Specification: VT table (golden waveform) and Open drain drivers, simplified correlation levels, and a revised test board. The specification serves as a communication vehicle and reference document. It is not perfect, nor does it cover IBIS Version 3.2 features. Bob asked for help regarding: Test cases for the specification Script/Code for the accuracy correlation metric (Bob has some Perl scripts that need finishing before he can upload them) Technical discussions in the IBIS Open Forum Constructive feedback Acceptance by Users, EDA and semiconductor vendors Pursuit of EIA approval Used by purchasing departments In summary, he needs more volunteers, approvals and, in the future, Version 3.2 enhancements. Bob Ross noted that we will have a technical discussion at the next meeting. The latest accuracy spec. (Version 1.2 document) has not yet been uploaded. AR - Bob Ross put Version 1.2 document on the eda.org website: http://www.eda.org/pub/ibis/accuracy/ IBIS OPEN FORUM SPICE TO IBIS SUBCOMMITTEE STATUS REPORT - Michael Cohen, IBM Michael Cohen introduced the Subcommittee members and the mission to recommend if the IBIS Open Forum should become responsible for the SPICE to IBIS translator code. The secondary mission is to draft some enhancement and bug fix requirements and suggest how to fund the project. Michael discussed the meetings and activities to date. He also presented Mike LaBonte's s2ibis flow to create an IBIS part model. Some general ideas so far are to make the tools be platform and SPICE simulator independent, have good documentation, and have maintainable code. Having a Web based tool is not a goal. Michael reported on feedback to date concerning the enhancement requests and bug reports. Michael also noted that the developer Michael Steer from North Carolina State University believes that the IBIS Golden Parser can be used for the next generation of s2ibis3. To summarize, the committee plans to compile a list of bugs and enhancement requests, make a recommendation to the IBIS Open Forum, generate a list of requirements, and help determine how to fund the project and get bids. SPITRAN: A GUI FOR S2IBIS2 - Mike LaBonte, Cadence Bob Ross introduced Mike LaBonte after commenting that the GUI interface source code is expected to be made publicly available and may also be offered for use in the s2ibis translator project. Mike outlined its general features: Written as a Java application - platform portable Audits SPICE files Prepares top level test circuits Prepares s2ibis control files Runs NCSU s2ibis2 For the remainder of the presentation Mike stepped through an application and showed the GUI templates. In response to comments during and after the presentation, Mike noted that what he is presenting is based on alpha code that will need improvements. He prefers multiple windows with simple questions rather than complex windows. Blank space can be used for explanations. The GUI focuses on doing one buffer at a time. Other code would be used to assemble the complete IBIS model. ADVANCED BEHAVIORAL TIMING ADJUSTMENT - Richard Mellitz, Intel - Adapted and Presented by Stephen Peters, Intel Stephen Peters introduced input buffer modeling by stating that Vinh and Vinl specifications and corresponding derating methods are no longer realistic for newer technologies. Actual input waveforms derate the data. One proposal uses a charge approximation based on finding the area under the input voltage versus time curve. Charge is assumed proportional to this area. Once the threshold crossings are determined, the flight time is adjusted for charge using an area based table. A similar adjustment method is used to determine actual ringback severity. This presentation prompted some discussion concerning the best approach for modeling inputs. D.C. Session indicated that he had considered a similar approach. He had presented at earlier meetings a different proposal based on actual time derating tables using an empirically derived 3/2 power voltage relationship. D.C. suggested he work with Stephen and Richard to agree upon an Input modeling proposal and to submit a BIRD for a Version 4.X extension. THOUGHTS ON EQUATIONS IN IBIS MODELS - Arpad Muranyi, Intel Arpad Muranyi provided background material to characterize SPICE, table driven, and IBIS (or behavioral) models. All models are behavioral. One differentiation is that SPICE models reveal process and circuit information, table driven models can hide the process information, and IBIS models can hide both process and circuit details. Arpad listed benefits of using equations: Equations are more compact Equations are more flexible and general Equations may be faster than lookup tables Equations allow easy scalability However, there can also be problems providing more burden to the model developer and simulator tool. Arpad gave examples where equations could be used in IBIS: Vinh, Vinl as a function of voltage, C_comp as a function of I/O pad voltage, scaling of I/V and V/T data, curve fitting of I/V and V/T data, etc. Equations can assist in the proper accounting of GND and Vcc currents for bounce simulations. This accounting also needs to includes how portions of C_comp are attached to Vcc and GND for both current allocation and possible decoupling effects. An actual simulation shows less bounce than predicted by the standard IBIS model connected to GND. Arpad also showed a "bleed through' effect that differ between PMOS and NMOS pullups. Others noted this as "clock through" or "forward feedback". Arpad also presented some ideas for considerations using equations for modeling transfer functions, power distribution on the die, and treating the model as a matrix - for the purpose of promoting more discussion on the subject. Transfer function could deal with complex impedances or conductances and other transformations. A possible 3 - model can be considered. EIAJ-IMIC Hideki Fukuda, Hitachi Hideki Fukuda, Chair of the I/O Interface Model Project Group under EIAJ in Japan provided much material. Some points are highlighted below. As an overview Fukuda-san gave the goals and history of the activity. The group is positioned under the Technical Standard Center along with a Package Electrical Characterization Project Group. Activity and numerous meetings with the IBIS Open Forum began in August, 1996. One immediate goal is to release Draft Version 1.2 in June, 1999. Fukuda-san gave a general technical overview description of the I/O model, IC, and Board components and of the table SPICE format. IMIC can be used for signal integrity, power integrity and (in the future) EMI simulations Some comparisons between IMIC and SPICE simulations for signal integrity and power integrity situations. Table SPICE simulations performed faster, but Stephen Peters questioned that since some of the results were done using different SPICE simulators the algorithm differences may also contribute to speed differences. However, good correlation was demonstrated for some test cases with coupled ground and power lines. Future work consists of Creating application notes - Signal Integrity of complex buffers - Power/ground bounce - Package electrical characterization Dealing with new technologies - Release an EMI model - Characterize new types of packages - Model a DRAM module Fukuda-san outlined an approach for handling EMI emission form a board: Use terminal currents to find the magnetic field of the circuits of the IC. Model terminal currents by transforming a time varying resistor into a voltage controlled MOSFET transistor Simulate EM emission from the board through its cables The simulation and modeling environment was classified into the Behavioral World and the Netlist World. SPICE, IMIC, Netlist IC simulators and Netlist PCB simulators fall in the Netlist World. IBIS and Behavioral based PCB simulators fall into the Behavioral World. Some Netlist PCB simulators now support IBIS, and IBIS models are being generated from s2ibis conversion. IMIC models fall in between SPICE and IBIS models, and IBIS models could also be generated from an IMIC to IBIS converter. IMIC models could support Netlist Based PCB Simulators. Fukuda-san sees an expansion of IBIS to support IMIC and some of the Netbase simulation environment. He concludes that such a move would benefit all parties - the electronic equipment industry, the EDA industry, and the IC industry. He also concludes that joint work by IBIS and IMIC could improve the silicon interface in PCB simulation. OUTLINE OF ECALS-2 PROJECT AND INVESTIGATION ON EMC/EMI SIMULATION MODELS FOR NON-ICS - Atsuji Itoh, Matsushita Atsuji Itoh, Chair of WG1 for Information Standardization showed ECALS-2 organizational structure. The overall goal of ECALS-2 is to standardize component information and to establish information exchange protocols. Funding is provided by MITI - Japan's Ministry of International Trade and Industry. The WG1 activities are Standardization of Dictionary and EDA model for electronic component information. One of its missions is to promote the EDA mode Representation standard (EDA Simulation Model, Logic Symbol, Footprint, etc.) Another group (SWG12) is involved with confirming the validity of IBIS and IMIC models for non-IC components and provide suggestions regarding IBIS and IMIC. The primary application is EMC/EMI simulation for digital consumer electronics and mobile applications. The consumer electronic design is moving toward rapid digitalization, speed (time to market and shortened lead times) and increased high speed, high density PCBs. Innovations are being made in the design processes, but it continues to be difficult to get simulation models of any format (IBIS, IMIC, SPICE, etc.). One focus of the WG1 group concerns non-IC EMC/EMI models for passive components, connectors and discrete semiconductor devices. IBIS is currently weak in comparison to SPICE for models of EMI filters and discrete networks. IBIS can be used for power semiconductors. Some preliminary results of discussions with model providers and users were given. Some conclusions so far are: Any data format is acceptable (IBIS, IMIC, SPICE), Effort must be made to expedite format standardization and expansion of the range of application, Need a checking tool for full EDA support, Standardization is required and relationships or migration between standard s need to be established between IBIS, IMIC, IEC TC93/WG6. SHINDENGENS'S ACTIVITY ON EDA Model AND SIMULATION OF ELECTRIC CIRCUIT (Added presentation) - Tsuyoshi Horigome, Shindengen Electric Mfg. Co. Tsuyoshi Horigome offered a brief presentation illustrating the user problem of getting EDA models in a timely manner. He showed an example simulating noise in a power module circuit. Model quality and cost are the primary issues, and it took nine months to get good models. FINAL COMMENTS: Bob Ross reminded people to get their SP-4557 comments in. IBIS Version 4.X Discussion was deferred. D.C. Sessions noted that the input and coupled package extensions were critical. Bob noted that the connector activity may relate to coupled package extensions. The next teleconference meeting was proposed to be Friday, July 23, 1999 to avoid conflicting with some vacation plans. NEXT MEETING: The next teleconference meeting will be on Friday, July 23, 1999 from 8:00 AM to 10:00 AM. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-56 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@viewlogic.com Senior Manager, Viewlogic Systems 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jonp@qdt.com Senior Scientist, Viewlogic Systems 1385 Del Norte Rd. Camarillo, CA 93010 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Signal Integrity Engineer, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 17641 NE 67th Court Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================