Date: 6/13/00 SUBJECT: 6/8/00 EIA IBIS Summit Meeting VOTING MEMBERS AND 2000 PARTICIPANTS LIST: 3Com Roy Leventhal Agilent (EEsof, etc.) Mark Chang Applied Simulation Technology Raj Raghuram, Norio Matsui, Fred Balistreri* Avanti Nikolai Bannov Cadence Design Mike LaBonte*, Todd Westerhoff, Ian Dodd*, Donald Telian, Patrick Dos Santos Cisco Systems Syed Huq*, Irfan Elahi, John Fisher Compaq [Bob Haller], Peter LaFlamme, Ron Bellomio, Shafier Rahman, Doug Burns Cypress (Rajesh Manapat) EMC Corporation (Fabrizio Zanella), Fairchild Semiconductor Craig Klem HyperLynx (& Pads Software) Matthew Flora*, Kellee Crisafulli*, Gene Garat, John Angulo*, Al Davis*, Lynne Green IBM Michael Cohen*, Greg Edlund, Jerry Hayes* Innoveda (Viewlogic Systems) Chris Rokusek*, Guy de Burgh*, Jun Tian, Cary Mandel, Brad Griffin, (Jon Powell) Intel Corporation Stephen Peters*, Arpad Muranyi*, Will Hobbs, Richard Mellitz, Charles Phares*, Meir Nakar*, Sigeti Gabi* LSI Logic (Larry Barnes) Mentor Graphics (& Veribest) Bob Ross*, Tom Dagostino*, Malcolm Ash, Kim Owen, Jean Oudinot, Sherif Hammad*, Hazam Hegazy, Weston Beal*, Ken Bakalar* Mitsubishi Shahab Ahmed, Carleen Murphy* Molex Incorporated Gus Panella Motorola Ron Werner National Semiconductor Milt Schwartz* North East Systems Associates Edward Sayre, Tony Sinker Nortel Networks Steve Coe, Calvin Trowell, Hassan Ali Philips Semiconductor D.C. Sessions, Todd Andersen* (& VLSI Technology) Quantic EMC (Mike Ventham) Siemens AG Bernhard Unger, Gerald Bannert SiQual Scott McMorrow, Wis Macomson Texas Instruments Stephen Nolan, Ramzi Ammar, Mac McCaughey, Thomas Fisher*, Jean-Claude Perrin, Jean-Yves Oberle Time Domain Analysis Systems Dima Smolyansky, Steven Corey Tyco Electronics (AMP) (Russell Moser) Via Technologies (Weber Chuang) Zuken (& Incases) Werner Rissiek, John Berrie* OTHER PARTICIPANTS IN 2000: Actel Corp. Silvia Montoya Advansis Mikio Kiyono Aerospatiale Matra CCR Lionel Dreux, Julien Boullie Alcatel (Lannion, Bell) Daniel Peron, Steven Criel Brocade Communications Robert Badal ECI Telecom Daniel Adar* EIA Cecilia Fleming* Fraunhofer Institute Michael Kurten Jet Propulsion Lab John Treichlew Hewlett Packard Paul Gregory Rockwell Collins Ron Hau Signals & Systems Engineering Tom Hawkins ST Micorelectronics Fabrice Boissiere, Pierre Saintot Sun Microsystems Victor Chang* Thomson-CSF Savenrio Lerose, Pascal Vaslin, Thierry Zak, Sylvie Lasserre Transfer Hans Klos, Wilco Hamhuis Xilinx, Inc. Susan Wu Independent, Consultant Hideki Fukuda* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode June 30, 2000 (916) 356-9200 6-234927 9698213 July 21, 2000 (916) 356-9200 6-234828 2232822 August 11, 2000 (916) 356-9200 6-234930 7474775 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS The IBIS Summit Meeting was held in Los Angeles, California the day after the trade show portion of the Design Automation Conference (DATE 2000) at the Hyatt Regency Hotel. The EIA IBIS Open Forum sponsored the meeting, lunch, and refreshments through membership funding. About 31 people representing 17 organizations participated. Bob Ross welcomed the participants. Everyone introduced him/herself. Semiconductor vendors, EDA vendors and users of EDA tools and IBIS models were represented. (Also, thanks to Cecilia Fleming and Guy de Burgh for handling the administrative and registration details.) All of the presentations and meeting documentation will be uploaded at http://www.eda.org/pub/ibis/summits/jun00/ The notes below give only some of the content and discussion. IBIS REPORT Bob Ross, Mentor Graphics Bob Ross introduced the general topics of the meeting. They consisted of Business and election of officers Connector specification discussion Future activities and ideas Other discussions Bob then gave a general status report. The EIA IBIS Open Forum continues to be active since 1993. It has 31 official members and about 350 to 400 people on the e-mail reflectors. The accomplishments for the previous year include releasing ANSI/EIA-656-A (IBIS Version 3.2), the ibischk3 parser. Also, the Accuracy Handbook was uploaded and the Connector Specification was released to the IBIS Open Forum for further work. These projects were initiated by the IBIS Users Group. The current IBIS projects include working on the Connector Specification, producing an IBIS Version 4.0 upgrade, and also working on a future version of IBIS. In addition the Open Forum monitors and works with other committees regarding IMIC, EMI, and JEDEC activities. Bob briefly summaries some of the future work. Bob then discussed the impact of IBIS. About 35 semiconductor vendors supply IBIS models from company Web links, and others directly through sales channels for an estimated 2,000 IBIS models. About 10-12 commercial IBIS vendors exist, amounting to over 11,000 IBIS models. Users also produce IBIS models and internal IBIS specifications and guidelines. Approximately 10 EDA vendors (behavioral and Spice) read IBIS models. Free and commercial IBIS tools are available. IBIS IBIS is frequently referenced in publications. Bob concluded that IBIS is well established. VHDL-AMS AND VERILOG-AMS, A DUAL TUTORIAL Ken Bakalar, Mentor Graphics Ken Bakalar, an active member of the VHDL-AMS and pending Verilog-AMS standardization activities, presented a general overview based on a full tutorial that normally would take longer to deliver. The full tutorial will be uploaded and covers much more detail than can be presented here. Ken defined a "Digital Simulator", "Analog Simulator", and a "Mixed-Signal Simulator" (AMS) and its partitioning into analog and digital elements and the synchronization between simulators. Ken gave a time-line and genealogy of the AMS activities. Both V*-AMS languages have these features (described in detail in the presentation): Extended structural semantics Mixed-signal simulation Continuous modeling extensions Frequency domain support Simulation control VHDL-AMS has these extras: Handling of initial conditions and discontinuities Mixed-signal initialization well defined Sequential or equation-based notation Sound mathematical foundations based on differential algebraic equation theory Formal definition Verilog-AMS has these extras: Automatic converter insertion at discrete/continuous boundaries Automatic resolution of signal flow/conservative connections Many built-in special case mechanisms Equation formulation uses controlled source notation Verilog VPI extension included Informal definition - users's manual Ken presented a diode sample in each language. (People raised some questions on details, and there are some editorial errors in the examples.) The uploaded presentations describe more structural details of both VHDL-AMS and Verilog-AMS. Ken closed with two examples, one describing piecewise defined behavior and the other describing sample and hold. Several questions and discussions occurred during the presentation. One dealt with whether there existed a Spice to HDL and HDL to Spice path. (This was not clarified.) Ken responded to Arpad Muranyi that table based data could be handled. Ken responded to Chris Rokusek that partitioning of matrices for optimization could be done for ground plane analysis. Ian Dodd commented on possible convergence problems and that the initial value problem was not solved. Ken stated that there is no visibility of the time step, and this is good. Ken differentiated VHDL-AMS as concurrent (order does not matter) versus Verilog-AMS as sequential. MISCELLANEOUS BUSINESS Bob Ross reported that the official ANSI/EIA-656-A in Acrobat format for IBIS Version 3.2 can be found at: http://www.eia.org/eng/standards/default.htm Bob reported on several recent articles that reference IBIS models. "Ensuring Signal Integrity" by Jon Powell has an IBIS sidebar and appears in the June 2000 issue of Printed Circuit Design, pp. 12 -16 & 24. Also, "Signal Integrity Tips Ensure FPGA Designers Meet Critical Market Windows" by Lynne Green and Rick Ballantyne in the May 29, 2000 issue of Electronic Design, pp. 97-100 mention IBIS. A link to the article is: http://www.elecdesign.com/magazine/2000/may2900/desapps/1DESAPP1.shtml Bob reported that STMicroelectronics has Flash Memory IBIS Models at: http://www.eu.st.com/stonline/products/support/memory/flash/ibis.htm Stephen Peters raised the issue of SPAM mail on the IBIS reflectors. This was discussed briefly. The way to deal with it would be with a majordomo based list which allows only list members to send e-mail on the reflectors. The following officers received thank you recognition plaques presented by Bob Ross and Stephen Peters for their service and contributions during the 1999 - 2000 year: Chair, Bob Ross, Mentor Graphics Vice Chair, Stephen Peters, Intel Secretary, Guy de Burgh, Innoveda Postmaster, Matthew Flora, HyperLynx Web Master, Syed Huq, Cisco Systems Librarian, Jon Powell, Innoveda ELECTION OF IBIS OFFICERS FOR 2000 - 2001 Bob Ross then conducted an election for the 2000 - 2001 EIA IBIS Open Forum Officers, one position at a time, starting with Chair. Nominations for the various positions had been previously announced at the May 26, 2000 IBIS meeting, and Bob called for any additional nominations. For the uncontested positions, the vote was conducted by a show of hands. For the contested positions, the candidates gave brief statements. A roll call vote based on one vote per EIA IBIS Open Forum member company was conducted. During the election Stephen Peters withdrew for the Chair. position because of work commitments and an upcoming sabbatical. Michael Cohen was nominated from the floor for Vice Chair. The vote for Vice Chair. was Stephen 6, Mike 5, and 1 abstention. The Librarian position election was held between previously nominated candidates, Jon Powell and Mike LaBonte. The vote for Librarian was Mike 8, Jon 3, and 1 abstention. The following people have been nominated as officers for 2000 - 2001 Chair: Bob Ross, Mentor Graphics Vice Chair: Stephen Peters, Intel Secretary: Guy de Burgh, Innoveda Postmaster: John Angulo, HyperLynx Webmaster: Syed Huq, Cisco Systems Librarian: Mike LaBonte, Cadence IBIS CONNECTOR SPECIFICATION Kellee Crisafulli, HyperLynx Kellee gave reported on the Connector Specification progress. The goal is still to complete the Specification this year after incorporate the changes requested at the January 31, 2000 IBIS Summit Meeting and also after improving some syntax descriptions and explanations. The document will be issued in Word, Adobe and text formats. A Working Group has been meeting regularly, the last meeting on June 6, 2000. Kellee discussed ambiguous syntax changes. Both Lumped and Distributed formats are now supported, similar to the Electrical Board Description. However, this is being accomplished differently using a new [Derivation Method] keyword to indicate a Lumped or Distributed for the matrix section. Also, a multiplier Mult = xxx (versus Len = xxx) to provides scaling of both the discrete or distributed sections. There was some discussion regarding whether explicit units are needed and should be optionally added. The Swath matrix usage has been further clarified. Now the term "edge only" is used to designate edge rows or columns that are to be used only at the edges, and to be terminated by a given impedance when the Swath is positioned for an internal group of pins. This was discussed and illustrated. One problem was raised. A smaller x-y swath can be positioned within a larger X-Y grid such that only the top edge are aligned. It is ambiguous whether the left and right pins of the top edge swath should be treated as edge only pins. (Kellee thought that it should, but needs to clarify this.) Kellee listed other details. The file line lengths were set to a consistent 120 characters and a line continuation character is allowed for model sections and stubs. Kellee presented some examples showing the revised syntax. Kellee summarized the short term goals as Finalize the changes Vote on Verson 1.0 of .icm Ask for funds for parser development Update the examples Confirm the accuracy by comparing to real connector data, Spice data and IBIS Package model data. Future goals for Version 2.x are Add lossy modeling Add other topology support such as cross-over pins. IBIS FUTURES - AN UPDATE Stephen Peters, Intel Corp. After lunch, Stephen Peters introduce the IBIS Future discussion topic. The previous tutorial on VHDL-AMS and Verilog-AMS fell under this general topic. Stephen reported that the first meeting was a face-to-face meeting held in March 2000. The goal was to provide a path to a 'next generation' I/O buffer description language. So far the progress has been slow. Mike LaBonte will conducting Working Group teleconference meetings while Stephen is on a sabbatical. Stephen stated the general requirements: Keep the good stuff of IBIS Standardized description Protect intellectual property Document signal integrity parameters Continue support of board level (behavioral) simulators Expand the format and structure to fix problem areas Expandability and flexibility (versus fixed keywords) Enable accurate modeling of simultaneous switching outputs, power delivery, and package effects Support behavioral receivers Enable equation descriptions (including S-parameters) Stephen presented the Issues and Considerations: Nodal descriptions are a necessity Die interconnect (pad and pin) descriptions Power delivery and pin to pin coupling Connections for black boxes Macro language for creating new model prototypes Flexible and extendible and allows existing IBIS model to be reused Enables a wide variety of descriptions Public Key encryption a necessity?? Tool vendor specific encryption or Public/private key administered by the IBIS Committee Use XHML Syntax? In the discussion segments, people indicated that S-parameters could be regarded as a possible subset of the general notion of equation based descriptions. Some comments were made regarding the reliability of encrypted models. The encryption issue will be treated independently from the IBIS Futures Working Group discussions. People cited the advantages of building upon existing standards and formats versus inventing a new format and also on prototyping the future work. OVERVIEW OF XML Mike LaBonte, Cadence Design Systems Mike LaBonte gave an overview tutorial of XML. He gave these definitions: Meta-language: SGML Standard Generalized Markup Language XML eXtensible Markup Language (subset of SGML) Language: HTML Hypertext Markup Language VML Vector Markup Language Mike then illustrated XML and XML editing tools. The key points of XML are: XML is a simple meta language - a basis for creating languages Unrecognized elements are easily ignored, since opening tags are always balanced by a closing tag Tools for working with XML are common Part of XML is the Document Type Definition (DTD). Its key points are: Hand out a DTD as your file format specification XML tools will automatically validate XML content against DTD DTD reference can be a URL to the "master" DTD Mike discussed and illustrated an eXtensible Style Language (XSL). Its key points are: XML data can be converted to HTML, or any other format XSL processors are built into browsers Report views can be altered by modifying the XSL file, without changing the tool that produces the data Mike listed some XML projects for EDA: Silicon Integration Initiative (Si2) QuickData - web part searches Pinnacles Component Information Standard (PCIS) Timing Diagram Markup Language (TDML) E-Tools EdaXML - EDIF replacement ChipData iParts Miner - extract part data from PDF, etc. Mike illustrated XML display using Internet Explorer 5 (and planned for Netscape 6), collapsing sections to hide data, and editing with XML Notepad. A number of comments were made during the presentation. An XML version of IBIS would eliminate the need for an IBIS parser to check syntax. Only value checking would be needed. Other tools may work with or export markup language formats. Mike is submitting examples of IBIS Syntax as part of uploaded presentation. A MACRO LANGUAGE FOR IBIS Al Davis, HyperLynx Al Davis had presented some draft documents at the January 31, 2000 IBIS Summit Meeting. The macro language gets around the IBIS fixed syntax problem (and BIRDs) and also is compatible with nodal representation and with the familiar aspects of IBIS. It is backwards compatible with IBIS. The circuit topology can be defined in the language. Al illustrated this with a simple Vsource, Rsource variable voltage and variable resistance driver model. The language includes inheritance, correlation (typ/min/max) and conditionals. It contains some basic Spice elements (R, L, C, V, I, E, G) and some Spice extras. Also some Non-Spice driver, trigger and alarm elements and some programming (assert, define, export, if, inherit, local and select) elements can be added. For receiver modeling, Al added fixed delay (digital or analog), variable delay (digital or analog) and analog behavioral blocks (gain, filter, integrate). Other elements for compatibility with driver schedule and submodels include reshape (digital) and array of components. IMIC style transistors and transmission lines can be considered. Currently, the macro language is 100% with IBIS Version 3.2. More study is needed for receivers. Pad to pin details need to be addressed. So far, one meeting and one teleconference meeting have been held. More meetings are now scheduled. GENERAL DISCUSSION During and after the presentation, a general discussion occurred on all topics. A few comments are captured here. Arpad Muranyi commented that the nodal connectivity and building block approach is natural to the application. Al Davis commented that the macro approach could be an extension to Spice. Fred Balistreri commented that mixed mode simulation was still not a reality because of iteration problems. Someone comment that IMIC could serve as the starting point. It has the Spice like syntax, and IBIS data sheet information could be added. A macro language would serve all vendors. A set of primitives may be implemented differently (or not implemented) by different vendors. Milt Schwartz stressed that application engineers often do the model development. The device design engineers are not involved, and the reference Spice models are usually not available. So model developers should have an easy, familiar, simple language. John Angulo commented that Verilog-AMS and VHDL-AMS were verbose syntaxes. An advantage with moving forward with a macro language approach is that the Spice and IBIS syntaxes are familiar to the model developers. All of the approaches need to be prototyped. Michael Cohen is interested in working with someone (Ken Bakalar) on a VHDL-AMS implementation of IBIS. The XML implementation of IBIS can also be checked. FUTURE MEETINGS Bob Ross closed the discussion by noting that several teleconference meetings have been scheduled. The next teleconference meeting will be held on June 30, 2000 and conducted by Guy de Burgh since both Stephen Peters and Bob will be out. (They still may call in.) The next IBIS Summit Meeting is scheduled on Thursday, September 14, 2000 in Worcester, Massachusetts at the same time as the PCBEAST 2000 conference. Mike LaBonte will host the IBIS futures group teleconference Working Group meeting on Wednesday, June 14, 2000. The Connector Specification Working Group will continue meeting, but the next date has not been scheduled. NEXT MEETING: The next teleconference meeting will be on Friday, June 30, 2000 from 8:00 AM to 10:00 AM. Guy de Burgh will be conducting the meeting. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Mike LaBonte (978) 262-6496, Fax: (978) 446-6798 mikelabonte@cadence.com Senior Technologist, Cadence Design Systems 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008 angulo@hyperlynx.com Development Engineer, HyperLynx, Inc. 114715 N.E. 95th Street Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org/eig/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================