Date: 2/2/01 SUBJECT: 1/29/01 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 2001 PARTICIPANTS LIST: 3Com (& CommWorks) Roy Leventhal Agilent (Mark Chang) Ansoft Corporation (Eric Bracken) Applied Simulation Technology Raj Raghuram*, Norio Matsui*, Fred Balistreri* Avanti (Chen Hongyu) Brocade Communications Robert Badal* Cadence Design Ian Dodd* Cisco Systems Syed Huq*, Lungfu Chen* Compaq Peter LaFlamme*, Ron Bellomio*, Quang Dam* Cypress (Rajesh Manapat) EMC Corporation Brian Arsenault*, Jinhua Chen* Fairchild Semiconductor Adam Tambone* IBM Michael Cohen*, Greg Edlund, Wes Martin*, Yeon-Chang Hahm*, Bill DeVey* Innoveda (& HyperLynx) Guy de Burgh*, John Angulo* Intel Corporation Stephen Peters*, Arpad Muranyi*, Dave Lorang, Michael Mirmak, Qinglun Chen*, Will Hobbs* LSI Logic Larry Barnes* Mentor Graphics Bob Ross*, Tom Dagostino*, Chris Reid*, Mike Donnelly*, Hazem Hegazy*, Tony Dunbar*, Griff Derryberry*, Dan Lake*, Sherif Hammad*, Mohammed Korany*, Weston Beal* Micron Technology Randy Wolff, Yong Phan Mitsubishi (Tam (Tom) Cao) Molex Incorporated Gus Panella*, Brian O'Malley* Motorola (Ron Werner) National Semiconductor Milt Schwartz* Nortel Networks Calvin Trowell North East Systems Associates Edward Sayre* Philips Semiconductor Zack Ciccone* Quantic EMC (Mike Ventham) Robinson-Nugent, Inc. (Alexander Barr) Siemens AG Bernhard Unger*, Helmut Katzier* SiQual Scott McMorrow*, Rob Hinz*, Bernard Voss*, Chris Brewster* Texas Instruments Thomas Fisher*, Stephen Nolan*, Ramzi Ammar* Time Domain Analysis Systems Dima Smolyansky*, Steve Corey* Tyco Electronics (Russell Moser) Via Technologies (Weber Chuang) Zuken (& Incases) (Werner Rissiek) OTHER PARTICIPANTS IN 2001: Actel Corporation Silvia Montoya* Acuson Kim Helliwell* AMCC Jeff Smith* Apple Computer John Figueroa* ASIS Ltd David Wright* EIA Cecilia Fleming FCI Sercu Stefaan* Foundary Networks Bertram Chan Framatom Conectors Danny Morlion* Fujitsu Ltd Tadashi Arai*, Takeshi Murakami* Huawei Technologies Rachild Chen* Hyundai Electronics Jongho Kang* Intrinsix Corporation Steven Chin* Nokia Tapani von Ravner* Oak Technology Darmin Jin* Plexus Technology Group Joseph Socha* Signal Integrity Software Douglas Burns*, Barry Katz*, Walter Katz* STMicroelectronics Peter Hirt* Xilinx Susan Wu* Independent, Consultant Al Davis* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode February 16, 2001 (916) 356-9200 2-508083 4216977 March 2, 2001 (916) 356-9200 2-508084 6782941 March 16, 2001 European IBIS Summit Meeting - No Phone Bridge All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS AND MEETING QUORUM The IBIS Summit Meeting was held in Santa Clara, California at the Santa Clara Convention Center. About 72 people representing 35 organizations attended. The notes below capture some of the content and discussions. The meeting presentations and other material will be uploaded at: http://www.eda.org/pub/ibis/summits/jan01/ Bob Ross opened the meeting by asking everyone to introduce themselves. The group was well represented by Semiconductor and EDA tool vendors and users of IBIS models. Also several people from EDA commercial IBIS model providers and EDA consultants attended. Several people were also involved in other official standards bodies, some of which are considering using IBIS models for simulation models. Bob thanked DesignCon for providing the meeting room, refreshments and the Booth as part of our Associate Sponsorship of DesignCon. The IBIS Open Forum is mentioned in the literature. Bob thanked National Semiconductor for providing the hot lunch and Milt Schwartz for taking care of the local arrangements including providing copies of the presentations. Bob thanked Applied Simulation Technology for loaning an LCD projector. Bob thanked Guy de Burgh and Innoveda for taking care of the booth backdrop and handling the member signs. The IBIS Booth is #861 on the show floor. Finally, Bob thanked the presenters and participants for attending. IBIS TODAY Bob Ross, Mentor Graphics Bob Ross briefly noted the current IBIS activity: Ongoing Version 3.2 activity including ibischk3 Version 3.2.6 and more BUG processing. IBIS Version 4.0 BIRDs being processed Connector Specification (Version 0.960 has been uploaded) Future "IBIS-X" We are also tracking other activities including EIAJ IMIC progress, JEDEC activity and European TC93 WG6 EMC/EMI activity. We are also noting that there may impacts from other standards. The meeting today progresses from present to futures: Current IBIS Model Development and Validation Future Needs Connector Specification Progress and Discussion Future IBIS-X Progress and Discussion Other Topics and Discussions Bob then asked for any new topics. Ian Dodd's report on HTML format for IBIS will included as part of another presentation. IBIS DOCUMENTATION FOR ACME ENGINEERING Scott McMorrow, Siqual Corporation Because of equipment availability, Scott McMorrow started first. He stated that his presentation was a reduced form of an actual report on a model he developed for a customer (with names changed). It shows a process for developing and validating IBIS models. The first problem is gathering all of the specification and Spice model information. Sometimes initial information is incomplete, so this process may take several weeks. The IBIS model are developed by using internal tools based on improvements to the North Carolina State University s2ibis2 utility. Once completed, the model is checked against several test circuits similar to those in the IBIS Accuracy Report. In particular a transmission line with a small capacitive loads are used. The Figures of merit similar to those in the Report are given with the model. Scott expects values in the range of 97% to 99% for released models. Scott mentioned that the major EDA simulators that process IBIS models give essentially the same results. He showed examples of IBIS buffer simulation overlayed with Spice model simulation. Some differences were based on DC errors in the I-V data. Sometimes waveform mismatch between some expected DC starting and ending values and those documented in the waveform tables caused some overshoot glitches. The other main source of mismatch were related to the number of points in the V-T tables. IBIS has an overall 100 point limit that sometimes must be allocated between the different time shifted typ, and max columns. He had observed that with 33 points he may get 6% error in correlation. Scott indicated that, if necessary, more points can be extracted and 100 points per column and can achieve 99% correlation. With 256 points, correlation is excellent and delays are with picoseconds. Scott extracts the die capacitance from the model. A wrong die capacitance provides the second largest source of error, especially at the receiver where the reflected amplitude is doubled. He described two methods. One is based on the response to a current source. The other is based on simulation of a driver and receiver and use Spice to find the value through optimization. Scott illustrated these points by showing overlaying Spice simulation and IBIS model simulation examples and noting some of the mismatch details and the probable reasons for the deviations. Scott agreed with a comment from a participant that the correlation metric number itself could depend on the length of the period (and the corresponding amount of overlaying data). Visual inspection for differences should also be done. Scott concluded that IBIS model simulation can be as accurate as Spice model simulation. Other variables such as actual board impedances contribute far more deviation in actual measurement to simulated results than the accuracy deviations discussed in the correlation study. THE JOY OF WEB MODELS Tom Dagostino, Mentor Graphics A customer had asked Tom Dagostino to "QC" (do a quality control check) a set of IBIS models needed for a project. About 20 of them were obtained directly from semiconductor web sites. Most actually were quite acceptable and may have needed only minor, easy to do addition or corrections such as adding threshold and timing values to some models. However, Tom had three really bad examples to share. The model names and vendor names were changed to protect the guilty! While the review process involves more steps, the models illustrated in the presentation failed either or both the ibischk3 and visual inspection check. The first model was a clock driver that had serious ibischk3 mismatches for rising and falling waveforms and I-V data. Visual inspection revealed that the pulldown table had zero current in the active region, as the source to the problem. A visual inspection also revealed that C_comp value was constant for all three cases: typ, min, and max. Tom reported these problems to the manufacturer, and after the second call he received a corrected model that was satisfactory. The second model was documented as a SCSI terminator. It passed ibischk3 with zero errors. However the model type was listed as Output complete with [Pulldown] and [Pullup] tables and [Ramp] data. The manufacturer has been contacted and stated that they would pass the information on. However, the manufacturer has not responded. The third component had at least several bad models. A model named as an _in model with a signal_name and Model_type Output had ibischk3 waveform errors. Closer investigation showed a number of interesting aspects: Vinh and Vinl were defined; the typ, min, max temperatures were not correct; and the I-V table data contained zeros in the normal operating regions. Also, the [Ramp] data contained zeros. Another _in model was documented as an I/O model with weak [Pullup] and [Pulldown] data and more [Ramp] data problems including negative time. Another had a constant voltage [Falling Waveform] table. A model, really documented as an _out model, had meaningless and unrealistic conditions regarding the content of the data: a "rough approximation" to lab measurements, and a max condition that was not consistent with the IBIS definitions. It passed ibischk3, but with waveform warnings. One source of warning was a repeated voltage value. Some tables had strange values inconsistent with typ, min, and max values. This time the [Pulldown] table had -0A values and [Ramp] data values of 0. For this component, the manufacturer has not yet responded to Tom's feedback. Tom concluded that some model developers need to do a better job in making models and QC'ing them before they are released. LVDS MODELING Hazem Hegazy and Mohammed Korany, Mentor Graphics Mohammed Korany reported on the problems associated with creating IBIS models for LVDS differential driver buffers with internal differential terminations. The basic problem is to extract the proper DC I-V data. He reviewed several existing methods and then two new proposals. The last proposal gave the best results. First Mohammed reviewed LVDS. He then reviewed two methods that have been proposed. The first one dealt with a voltage sweep at PAD with PADN connected to R_load and Vref. The second method used a mirrored negative current source at PADN. A third method was also presented where mirrored delta voltages are applied at PAD and PADN. All of these methods worked for 50 ohm loads and provided nearly overlaying IBIS and Spice simulations. Some DC offset was observed with 100 ohm terminations. However, all methods gave DC offsets when internal differential terminations existed in the LVDS model. Mohammed accounted for these offsets by showing the mathematical distribution of currents during extraction of the model. Proposal I was similar to Method 3, but had the voltages attached to a Vmid value derived from averaging the low and high state voltages. This produced better results but still showed DC differences with internal terminators and the load equal to 100 ohms. It only supported the using the R_fix value load. Proposal II used mirrored resistance changes with resistors connected to the Vref value. This produced overlaying simulations for all cases. Mohammed showed overlaying simulations with a test circuit where the differential, internally terminated buffer was driving a lossy, coupled differential line into a receiver load. The results overlaied well for all differential conditions. Mohammed noted that one could remove the internal differential resistor as another approach. Bob Ross noted that we may not know exactly the internal resistor (if the driver does not have a high Z or input mode or if the Spice model is encrypted). Several people noted that the examples showed larger differential voltage swings than specified for LVDS. Mohammed stated that this was from an ASIC produced by one vendor. The methods discussed are applicable to LVDS. Arpad Muranyi (several methods were referenced from his class material) stated that this was good information. He never did consider the impact of internal differential terminations. Ed Sayre stated that even other terminations including AC terminations may exist. It is important to get the model correct for DC and AC responses. Mohammed concluded that LVDS IBIS modeling needs high DC resolution LSI POWER AND GROUND MODEL FOR EMI SIMULATION Norio Matsui, Applied Simulation Technology and Hiroshi Wabuka, NEC Norio Matsui introduced the problem by showing several simulation comparisons between IBIS Simulation, table Spice (IMIC) simulation and Spice (all done using the Applied Simulation Technology tool. Standard simulation of LVDS and PECL circuits work well. However, IBIS loses some detail with internal inverter circuits and also does not produce the same simultaneous switching output (SSO) responses for currents and voltages. ICs with complex internal structures cause unaccounted internal currents that need to be added to the model for ground and power modeling and EMI. For large scale integration (LSI), the conventional IBIS structures can be used for input and output. An internal current circuit is added between the input and output structures. Such an internal structure might represent a clock macro. The techniques for macro modeling can be: I/O IBIS or IMIC for I/O + Package Clock 10% consumes most power (highest frequency) Non Clock Behaves a filters/decoupling capacitors Norio described the procedures for macro modeling and showed some Spice and table Spice structures and also some IBIS EBD and IBIS I/O structures. The clock and non-clock model can be realized using a cascaded double IBIS I/O for the dynamic portion and a set of RC networks for the non-clock static portion. Norio showed a final circuit containing double inverters for the middle stage. Using this approach, Norio showed accurate correlation between the IBIS/EBD and table Spice (IMIC) models for current waveforms. There was some loss in accuracy when he simplified the model using only four IMIC transistors. Norio also showed accurate comparisons simulated and measured peaks of near field EMI. Arpad Muranyi questions whether splitting C_Comp into components to different rails might improve the accuracy for the simplified model. Also die interconnect details were not simulated in this study. SCSI COMPENSATION MODELING Larry Barnes, LSI Logic Larry Barnes introduced himself as co-chair and technical editor of a Ad hoc Working Group involved in T10. T10 is a Technical Committee of the National Committee for Information Technology Standards (NCITS). It was formerly known as the X3 Committee. NCITS is accredited by and operates under rules approved by ANSI. Larry showed the membership and gave some background on the Small computer Systems Interface (SCSI). A technical synopsis of SCSI configurations include: Bus structure with 27 data, 8 ground, 4 termination power, 2 reserved lines 68 conductors, 90 - 120 ohms, single ended or differential 25 meters point-to-point 12.5 meters with 16 stubs Allowable loading of 30 pF / stub Larry presented a number of issues that produce data errors associated with 320 MBytes/second transfer rates, decreased setup and hold time, intersymbol interference, decreased cable charge time, and 16 capacitively loaded stubs. The eye diagram without compensation has decreased, and the worse case situation has no opening. Larry proposes a solution which produces a very acceptable eye diagram: Run length encoded compensation at the transmitter Transmitter overdrives unless two or more data bits are sequentially the same value Second data bit and subsequent bits of the same value have the drive level reduced Drive strength, rise time and fallback are programmable Training pattern upon initialization with bit rate negotiation Larry is writing an ANSI/NCITS Technical Report on SCSI Signal Modeling to document the details of the solution. The Working Group has selected IBIS a the data exchange format for: Semiconductor device models Termination models Connector models (when codified) The Working Group would like to continue to use IBIS if fallback modeling can be accomplished. Currently IBIS Version 3.2 can be used for SCSI devices for: Single-ended models High voltage differential models Low voltage differential models SCSI 320 Mbyte/s driver characteristics require a fallback model: Differential current mode transmitters Negotiable data rates Multi-level parallel positive and negative current drivers Uses programmable fallback Fallback cannot be modeled in IBIS Version 3.2: Driver schedule keyword is close Needs bit position dependency, not time Future may include overdrive past first bit Needs accommodation for parallel current mode drivers Larry proposes adding a [Fallback Schedule] keyword: Similar in construction to [Driver Schedule] Describes switching sequence fallback modeling Delay parameters are in terms of bit times Accommodates typ, min, max conditions Differential operation Two current sources and sinks for each line This will cover the next generation of SCSI and IBIS futures through 2003. Subsequent generations may include phase encoding. Larry hopes that this will fit in the future of IBIS. Larry welcomes IBIS participation in this Working Group. A draft work in progress specification is available at: http://www.t10.org LUNCH The Group broke for a delicious buffet lunch sponsored by National Semiconductor. CONNECTOR SPECIFICATION Gus Panella, Molex Gus Panella reported on the progress of the IBIS Connector Specification. There have been some delay because of the loss of a key member (Kellee Crisafulli), limited participation, holidays, and working with a big document. However, the Working Group has been improving the descriptions and clarifying ambiguous syntax. Gus reported on some of the changes: Removal of Physical Map because of unnecessary complexity Distinction of Side_A and Side_B pin maps Clarification of [Redistribution] Specific to mean comments are in the Header section Some number of pins, rows, and columns ranges to document physical limits More [Cn_Row_Swath] and [Cn_Column_Swath] distinction and edge definitions and usage Gus reported that Ian Dodd provided a C-style syntax to describe the pin map information as a function of ROW and COLUMN entry specified by the EDA tool. Ian gave the brief description (given below) at this time. Gus stated that the current discussions involve following the IBIS-X group header suggestions, where practical. These include bracketing the header with [Begin Header] and [End Header] keywords. Gus asked if the [Source] keyword should be required. It is not required in all other documents. The consensus was mostly in favor on not making it required after some meeting discussion. Gus also asked about using " " (space) or "_" (underscore) between keywords, but this was clarified as an documentation editorial detail, not a functional detail. Both conventions will be supported. The work in progress (Version 0.960) of the Connector Specification has been uploaded for review. Gus closed by mentioning some short term goals. He concluded that the document is reaching technical completion. Bob Ross added that he plans to release the document for full IBIS Committee technical review and comments while the editorial cleanup of the document is being done. The document will go through formal review processes for EIA IBIS Open Forum approval, and further review processes (including a 90 day formal public review) for EIA ratification. IBIS CONNECTOR SPECIFICATION: PRELIMINARY PROPOSAL FOR A PIN NAMING LANGUAGE Ian Dodd, Cadence Design Systems As part of the Connector Specification presentation, Ian Dodd displayed and discussed aspects of a proposal for pin naming language. The main points of the proposal are: It adopts C - like code style including C style formatting statements It predefines certain variables ROW, COLUMN, SIGNAL_NAME, and PIN_NAME It presumes all variables are integers and do not need to be declared It has some simple math operations and conditionals It can easily specify incrementing characters through addition Ian showed some applications including one where a row was missing. He stated that the proposal might be compatible with the IBIS-X macro language. One issue is whether they should be aligned. The text formatting might be needed for the macro language. One pending decision is whether the C style of ending lines with semicolons should be done in the pin naming language. AN API FOR IBIS?? Al Davis, Consultant Al Davis gave an informative presentation on an application programmable interface (API) for IBIS. He defined an API as: A binary interface for models It supports portable models external to the simulator It provides the ultimate generality and intellectual property protection Al listed a number of issues: Type of interface Operating System differences Language differences Simulator differences Uses beyond simulation Hard to make portable (easy for one simulator) The interface can be dynamically linked object modules (faster, but harder to develop and less portable) or a separate application or applet (slower, but more general and portable). Al prefers the executable approach. He listed some advantages and issues. It should support different types of simulators ranging from Spice-like, mixed-mode, transmission line / tree based, gate level, and HDL. It should also support more than one simulation. There was some discussion on whether API's would be repeated if the model was used several times. This needs to be clarified. The functions needed for an API are: Parsing and printing the calling netlist Pre-processing Predictor step Evaluation Gather and scatter Review step (iteration and step control) Probes Status queries Plus about a dozen more Normally the user would use other tools to write the functions including VHDL-AMS, IBIS-X, etc. The simulator developers would do the work since the complete understanding of simulator internals is needed. Al concludes that an API is needed, but it will take coordination between EDA companies. It has potential beyond IBIS. IBIS FUTURES GROUP UPDATE ON IBIS-X Stephen Peters, Intel Corporation Stephen Peters, who is serving as Chair or the IBIS Futures Working Group introduced the progress on IBIS-X. He listed the goals: Provide extensible syntax Enable complex/coupled package descriptions Maintain backwards compatibility (IBIS Version 3.2) Support some additional requirements (equation based modeling, HTML viewing, public key encryption) Briefly, IBIS-X provides the following: Nodal based package description (die interconnect pin to pad, power delivery, and pin coupling) Macro language for creating new model types The current status is: Al Davis has implemented IBIS Version 3.2 in a macro language The Working Group meets bi-weekly on writing a formal specification: Overall IBIS-X Specification Library Guide Programmers Language Reference Manual (LRM) expected in months Work remains on the die interconnection section Stephen introduced some current issues: Alignment with the Connector Specification Case sensitivity in .ibs files (need to create rules for capitalization if it is supported. HTML support Support of more general equations and black boxes such as the Berkeley Spice B element Where does the API fit into this? (Later Al Davis raised the case sensitivity issue with the group. The majority indicated preference for removing the requirement.) PROPOSED NEW DIRECTIONS FOR IBIS PCB SIGNAL INTEGRITY MODELS Ian Dodd, Cadence Design Systems Ian Dodd provided an overview of IBIS today and future needs. He gave the brief history of IBIS development and features and described its well-known modeling advantages. He also listed some limitations: Feature changes require the slow process of adding new keywords The rate of requests for feature changes is accelerating Models assume a fixed topology The present standard is inadequate for todays needs in: Input transition detection Simultaneous switching noise Power delivery Coupling within packages Ian listed a number of goals, similar to those discussed by Stephen Peters. IBIS-X for the next generation should: Extend the data sheet Add a new structure template Ian illustrated the extended data sheet (similar to IBIS) and noted the structure details and topology. He also listed a number of circuit elements for IBIS-X Ian also discussed and illustrated how IBIS and IBIS-X can be made compatible with HTML. A feature is that lines with "<" in column one are assumed to be HTML formatting commands. Some details have to be worked out regarding some initial declarations. HTML can also be used to add separate graphics file pictures within IBIS files. Ian illustrated doing this using a portion of an example provide by Stephen Nolan. Scott McMorrow raised the concern that the Working Group might be working on fluff and not dealing with the critical issues. Ian responded that this issue was really not taking much time. Ian listed and discussed a number of advantages of IBIS-X: Extensible Allows reuse of structural template Data is separated from templates Devices in a wide range of logic families can share structural templates Can read existing IBIS models Nodal structure allows multiple levels of abstraction He also listed some concerns: High expertise is needed to create new IBIS-X templates Model developers will need to create more than one type of data sheet Simulation tools will have to be more intelligent in syntax checking. Model validation will be more difficult. Ian listed the future IBIS-X work and noted that there are still some open issues and concerns regarding the level of abstraction and whether exiting standards can be used. Ian concluded that IBIS-X is promising, but it will require increased sophistication of validation tools and training for model developers. IBIS-X PROGRESS REPORT Al Davis, Consultant Al Davis listed the progress: Some documents Working parser Tested with about 100 IBIS files Some bugs Generates partial Spice deck Al's goals are Doing simulations by March Also include the Connector Specification Produce a presentable version of the Specification by March He currently has a working demonstration. It can be downloaded (pre-alpha code for review). It can be found at: http://table.jps.net/~atd/ibisx.200101.tar.gz IBIS-X MACROLANGUAGE Al Davis, Consultant Al Davis reviewed a previous presentation on IBIS X. He stated that the basic simulator requirements were: Handling piece-wise linear (PWL) constructs Handling two-dimensional PWL tables (time and signal) Having a "trigger" to shift time tables Additional elements include generalized expressions for Voltage, current, charge, flux Multi-port block IBIS-X supports structure (a spice like description with expressions). IBIS already contains data with data sheet like information for tables and attributes. These were illustrated. Other structures Al illustrated were conditionals (if), time dependent tables and triggers, an IBIS compatible driver element, a new foreach statement, and an alarm, and value expression. A number of points were discussed including having a floating gnd versus absolute 0 voltage ground and having $ before variables. CONCLUDING ITEMS Bob Ross again thanked the sponsors of the meeting and also the presenters and participants. Bob stated that the next teleconference meeting is planned for Friday, February 16, 2001, and the following one on March 2, 2001. Actions are still needed for issuing BIRD65.2 and BIRD68.1 prior to voting on these. Bob reminded us that the European IBIS Summit Meeting is scheduled for Friday, March 16, 2001 in Munich Germany in a hotel near the Design Automation And Testing in Europe DATE 2001) conference and exhibition. The four co-sponsors are Cadence Design, Innoveda, Mentor Graphics, and Zuken (Incases). The first notice was sent out at the end of January 2001. So far Bob has about three or four presentations proposed so far, so he expects this to be an all day meeting with a free lunch to participants. Bob asked if there were any questions or issues to discuss briefly. Kim Helliwell asked about what was happening to the s2ibis3. Michael Cohen commented that after much debate we decided not to seek funding on the project because it would create a product that already competed with a commercial product. Bob added that there were other commercial modeling services as well. However, the project specification is still uploaded, and anyone can still work on it. NEXT MEETING: The next teleconference meeting will be on Friday, February 16, 2001 from 8:00 AM to 10:00 AM. BIRD65.2 and BIRD68.1 are scheduled for a vote if ready. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 stephen.peters@intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799 roy_leventhal@3com.com Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary) 1800 W. Central Rd. Mt. Prospect, IL 60056-2293 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008 jangulo@innoveda.com Development Engineer, Innoveda 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eigroup.org/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================