DATE: 04/08/04 SUBJECT: April 5, 2004 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 2004 PARTICIPANTS Ansoft Corporation (Eric Bracken) Apple Computer (To Be Determined) Applied Simulation Technology Norio Matsui* Cadence Design Systems C. Kumar, Lance Wang*, Patrick dos Santos Cisco Systems Sergio Camerlo, Syed Huq, Todd Westerhoff*, Mike LaBonte*, Stan Penner* Fairchild Semiconductor (Graham Connolly) Hitachi ULSI Systems Kazuyoshi Shoji Huawei Technologies (Jiang Xiang Zhong) Intel Corporation David Keates, Peter T. Larsen Wilson Leung, Michael Mirmak*, Arpad Muranyi*, Steve Peterson LSI Logic Frank Gasparik Matsushita (Panasonic) Atsuji Ito Mentor Graphics John Angulo*, Weston Beal, Ian Dodd*, Guy de Burgh, Stephane Rousseau, Eric Rongere, Gary Pratt* Micron Technology Paul Gregory, Randy Wolff Molex Incorporated (Gus Panella) Motorola (Rick Kingen) National Semiconductor (Lee Sledjeski) NEC Electric Corporation (Itsuki Yamada) North East Systems Associates Edward Sayre Philips Semiconductor (D.C. Sessions) Samtec (Corey Kimble) Siemens AG Eckhard Lenski, Manfred Maurer Siemens Medical (Acuson) David Lieby Signal Integrity Software Robert Haller*, Barry Katz Sigrity Raymond Chen, Jiayuan Fang Sun Microsystems (Tim Coyle) Synopsys (Hailong Wang) Texas Instruments Hector Torres, Jean Claude Perrin Teraspeed Consulting Group Tom Dagostino, Scott McMorrow*, Bob Ross* Time Domain Analysis Systems Steve Corey Zuken (& Incases) Ralf Bruening, Laetitia Simonian, Caroline Legendre OTHER PARTICIPANTS IN 2004: Alcatel Jean-Pierre Bouthemy Apache Design Yu Liu Bayside Design Daniel Lambalot, Kevin Roselle Conexant Garry Felker Cortina Systems Robert Badal EADS Olivier Maurice Edality Rob te Nijenhuis EFM Ekkehard Miersch Extreme Networks Lin Shen Fraunhofer IZM Ege Engin GEIA (Chris Denham) Green Streak Programs Lynne Green* Independent Kim Helliwell, Jon Powell INSA Etienne Sicard Netlogic Microsystems Eric Hsu North Carolina State Univ. Ambrish Varma Politecnico di Torino Igor Stievano Samsung Il Seong Silverback Systems Gil Gafni Sintecs BV Hans Klos In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode April 23, 2004 1-916-356-2663 4 470-5211 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- INTRODUCTIONS AND MEETING QUORUM The IBIS Summit Meeting was held in Boxborough, Massachusetts at the Holiday Inn in conjunction with the International Engineering Consortium's (IEC) DesignCon East 2004 Conference. The summit was co-sponsored by IBIS and DesignCon. 14 people representing 7 organizations attended. The notes below capture some of the content and discussions. The meeting presentations and other documents are uploaded at: http://www.eda.org/pub/ibis/summits/apr04/ Michael Mirmak opened the meeting. Michael thanked the IEC and DesignCon East for providing a room, noting that IBIS is a co-sponsor of DesignCon. Michael also thanked Robert Haller and Terry Roulic of SiSoft and Lance Wang of Cadence Design Systems for strong logistical support. He also singled out Lynne Green for her assistance with calls for papers and setting the agenda. Finally, Michael thanked the presenters and participants for attending. Michael asked everyone in the room and on the teleconference bridge to introduce themselves. The group was well-attended by semiconductor vendors and model providers (five), EDA tool vendors (five) and users of IBIS models (seven). Michael asked if there were any new issues or discussion items to add to the agenda. No issues were raised. PRESENTATIONS AND DISCUSSION TOPICS The rest of the meeting consisted of presentations and discussions. These notes capture some of the content and discussion. More details are available in the documents uploaded to the location noted above. IBIS CHAIR'S REPORT AND ROADMAP Michael Mirmak, Intel Corporation Michael reviewed the recent work of the IBIS Open Forum and IBIS community at large. The Open Forum has made stunning progress in advancing behavioral modeling over the past eight months. IBIS 4.1, which introduces links to Verilog-AMS and VHDL-AMS models into IBIS, has been approved. Thanks to Norio Matsui, the JEITA EDA Working Group helped promote IBIS 4.1 through an EDN Japan article in the April edition, focusing on consumer applications for IBIS modeling. Bidding for the IBIS 4.1 parser has begun, while an IBIS 4.0 parser has been completed and publicly released. Further, the IBIS Interconnect Modeling Specification (ICM) 1.0 was issued and a golden parser released to the public, under an open-source license agreement. The IBIS Quality Committee completed its Quality Specification, which is the subject of a later presentation. Despite a slow economy, Michael observed that finances continue to be strong, with 28 paid members and ten purchasers of (IBISCHK4) Golden Parser licenses. While IBIS Open Forum work has been successful, challenges still remain ahead for IBIS as a whole. Michael suggested that more corporate and industry-publication guidance be provided on the new languages linked to IBIS under version 4.1. Further, the Open Forum should continue to expand and enhance a global IBIS community; support of the European DATE summit must continue, but the Open Forum should also consider holding "Electronic Roadshow" presentations. Michael thanked the IBIS Open Forum participants and community members for their continued support. To explain the proposed IBIS roadmap. Michael summarized the history of IBIS parsers and IBIS specification releases since version 1.0. On average, a new parser version has been released 28 months after the final release of the corresponding IBIS specification. In addition, Michael noted that a new major IBIS release is approved every 24 months, on average. The Open Forum should be more proactive in seeking out and including support for new technologies, rather than waiting for industry adoption before including support in IBIS. To address this, a revived Futures Subcommittee has been chartered to develop IBIS and ICM improvements. A few have already been proposed: explicit digital states for 4.1 input ports, user-definable measurement and input threshold parameters, and formal links between ICM and IBIS. In addition, to better support the IBIS community in adopting new technologies and modeling approaches, Michael described the new Cookbook Subcommittee. Further, Michael elaborated on his "E-Roadshow" proposal. As the global economic situation still does not permit extensive travel, but globalization is still spreading in the industry, a new method is needed to assist and train IBIS users and model makers worldwide. The Open Forum should provide short training sessions, called "E-Roadshows," in time zones convenient to the US, Europe and Asia, featuring one or two summit-quality presentation and question periods. This would help bring state-of-the-art training to other parts of the globe while not incurring the costs associated with international travel. Michael showed a graphical timeline illustrating the most desirable milestones for these deliverables. Mike LaBonte commented that, for ICM, only a few companies generate connector-oriented models and even fewer generate the appropriate analysis tools. Scott McMorrow responded that organizations such as his can create accurate models 3-6 months after support is implemented in analysis tools. He suggested that EDA tool vendors, for both IBIS and ICM, should focus on implementing the specifications in order to generate more interest in creating and using models. Michael Mirmak suggested that this was a "chicken-and-egg" problem, in that tool vendors may not wish to risk development resources before demand is clear. Additional comments on tools focused on clarifying what specification features are supported under which tools. Few tools currently describe their support for IBIS in explicit terms. Some participants demanded tool test cases or standardized verification of support before a tool can claim to be compliant to a particular specification revision. Ian Dodd responded by suggesting that a trade-off exists between modeling devices better or modeling other features, such as traces. So far, EDA tool vendors have not always been successful at predicting popularity or usability of features. Many attendees agreed that, for both ICM and IBIS, accurate modeling cannot be done without non-ideal grounding, which few tools support. Scott McMorrow accepted the AR to produce a "talking points" document or presentation on the need for non-ideal grounding treatments in models and tools. Such a topic, along with I-t tables, would be useful for a future "E-Roadshow." A TOUR OF THE IBIS QUALITY SPECIFICATION Robert Haller, Signal Integrity Software (SiSoft) Robert reviewed the purpose of the Quality Committee and thanked Mike LaBonte for his contributions. He then provided an overview of the recommended checklist in the IBIS Quality Specification and the levels of model quality defined. Robert stated that some Quality Specification material is cross-referenced with the earlier IBIS Accuracy Handbook. The key idea behind the IBIS Quality document is its description of quality levels. A Level 0 model has passed the simple IBISCHK parser checks without errors. At Level 1, the model has additionally passed basic simulation testing with transmission lines and the like. A Level 2a model has been correlated in simulation with a transistor-level model. Robert suggested that parser BUG reports may be filed to include level one checks as part of the golden parser. Robert observed that comments within the model, labeled "|IQ," are used to document the various levels and the outcome of testing. A separate document is not intended to be created for distribution with the model. Robert also noted that the core IBIS data would not be changed by the IBIS Quality procedure. Several participants expressed concern that any significant checks outside of running the parser meant increased cost due to the time and data collection required. Robert provided a sample checklist template for use with individual models and also provided links for attendees to use to download both the template and the specification. He concluded his presentation by noting and thanking the committee participants. For additional information on the quality committee and to be included on the mailing list send mail to ibis-quality@freelist.org. The IBIS quality committee web site is available on the IBIS web page or at http://www.sisoft.com/ibis-quality IBIS HIERARCHICAL OVERRIDES AND BIRD88 Bob Ross, Teraspeed Consulting Group Bob Ross described hierarchical override as the primary means for which IBIS has expanded from the 8 page beginning to the current 140+ pages. Additions were made by overrides rather than conditional replacements around some cornerstones like EBD (later), [Component], [Package], and [Model]. This approach, needed by industrial functionality demands was the least disruptive. A motivation for the presentation is to continue the ideas underlying the [Driver Schedule] initialization statement in BIRD88. This presentation also relates to issues we have been discussing with the IBIS Quality Specification, Cookbook upgrade, Interconnect Model Specification (ICM), etc. The main benefits were to keep simple rules, keep IBIS looking the same, keep the parser simple, and keep original default structures. However, it is not always technically robust or correct. Redundant information is formatted that is wrong or confusing. Also inheritance of information becomes an issue ([Driver Schedule] vs. [Submodel]). Bob illustrated hierarchical overrides for packages, voltage rails, and thresholds. C_comp has exceptions where only its replacement can be given. [Diff Pin] has overrides on top of the [Model] subparameters and also can set [Model] states. However, [Model] initial states are central to IBIS and can be used for scheduled model initialization of [Driver Schedule] as originally intended according to BIRD88 details. Bob outlined the stated/unstated assumptions surrounding the [Driver Schedule] keyword in terms of documenting a full cycle of operation with each scheduled model. A number of rules emerged with IBIS based on these assumptions. Bob noted that the initialization table is now formatted from the [Model] state point of view that is implied in the Specification. Some initializations are not allowed. Bob concluded that hierarchical overrides are a basis for IBIS expansion and for interpretation of [Driver Schedule], as documented in BIRD88. ISSUES WITH C_COMP AND DIFFERENTIAL MULTI-STAGE IBIS MODELS Michael Mirmak, Intel Corp. Michael presented a detailed overview of implementation of standard differential buffers and pre-emphasis-enabled differential buffers for interfaces such as Serial ATA. These designs feature always-on current sources switched between transmit output pads. Pre-emphasis simply adds one or more current sources with additional current switching to boost certain data bits in output voltage. Many of today's implementations feature pre-emphasis only during the bit immediately after a transition from one logic state to another. Under IBIS, pre-emphasis buffers are implemented by tying two differential pairs together at the same pads, in a "wired-or" configuration. The input data stream for the pre-emphasis buffer pair is different than that used for the main pair. This raises issues related to C_comp, as tools will adjust the V-t tables of each buffer in each pair based upon a single C_comp value. If this value is incorrectly chosen, the loading of the wired-or configuration could be too large or too small. Michael suggested adjusting "out" the C_comp of the entire buffer from the individual V-t tables before the corresponding IBIS models are assembled and used in system simulations. The buffer capacitance would be added externally to the buffer. The example cited required larger-than-expected capacitances to match transistor-based model outputs. Further, a plot of capacitance vs. voltage and frequency indicated, as was known, that a single capacitance value may be insufficient for many high-speed applications. Such functions can be added to models using IBIS 4.1. CASE STUDY: USING IBIS BUFFER MODELS FOR PRE-EMPHASIS Lance Wang, Cadence Design Systems Lance summarized the essential approach to modeling pre-emphasis, using separate main and boost buffers, with stimulus patterns generated for the boost by inverting and delaying the main buffer's stimulus pattern. Pre-emphasis is becoming increasingly common for DSP applications. Lance's PCI-Express*-based example features a boost buffer scaled from the main by a fixed amount, expressed in dB. A fixed bit width and buffer pad capacitance are also supplied to the model as a whole. Equations convert the dB value to a scaling factor, which is applied to the I-V and V-t tables to generate the boost behaviors. Similar equations can be implemented under a variety of SPICE-compatible simulation tools. Lance showed output waveforms with pre-emphasis effects clearly visible, across a variety of different drive frequencies. Lance concluded by proposing that IBIS be expanded to include keywords expressing stimulus delay and scaling factors. These proposals would not explicitly address wired-or configurations outside of IBIS, but would allow direct control of pre-emphasis parameters with IBIS keywords. Todd Westerhoff expressed skepticism that a fixed bit-width could be used reliably with higher frequencies. Instead, a logical equation or other variable parameter should be used, so that the one-bit delay tracks the actual driven frequency. Michael Mirmak suggested this could be handled by IBIS 4.1 AMS equations. Robert Haller inquired as to whether a bit-width equation would adequately handle over-clocking if fixed-length V-t tables were used. The question was deferred until Arpad Muranyi could join and address it. Some participants asked about multiple-bit filtering architectures. Bob Haller in particular mentioned having seen designs with many bits of filtering depth, rather than the single one shown. A similar approach to Lance's could be used in such cases. Others inquired about SSO when 8 bit data was converted to 10 bits of output across a wide bus. Finally, the attendees discussed how internal terminations should be added to the model. Participants suggested adding it to clamp tables, exclusive of scaling, using a third wired-or buffer containing only termination information or using a G-element to describe the termination behaviors. A VHDL-AMS PRE/DE-EMPHASIS BUFFER MODEL USING IBIS V3.2 DATA Arpad Muranyi, Intel Corp. Arpad continued his series of VHDL-AMS buffer examples by showing how pre-emphasis can be implemented using IBIS 3.2 data under VHDL-AMS code. He summarized the operation of pre-emphasis designs in terms of multiple current sources switching between differential output pads. The VHDL-AMS model for this circuit builds upon the earlier VHDL-AMS model for differential behavior, including a single digital input, a digital clock input and two analog I/O ports to express true differential behavior. The code permits users to select initial output conditions plus the type of input triggering (rising edges, falling edges or both). The one-bit delay and inversion routines needed to control the main and boost stimuli based on a single stimulus pattern are also included. Finally, a separate scaling coefficient is provided to scale the I-V tables provided for the main to generate the boost curve data. Future work will include data-dependent C_comp compensation, in line with Michael Mirmak's earlier presentation. Arpad expressed concern that the effects of the buffers loading each other has not yet been adequately investigated. An upcoming presentation will outline the model's behavior versus other tool implementations, including SPICE. OTHER DISCUSSIONS AND AD HOC PRESENTATIONS Current and power estimations, particularly I-t tables, featured prominently in the general discussions among the participants. Robert Haller suggested that the recent proposals to the Open Forum were related to core current events, while technical discussions at earlier summits focused on buffer-only current distribution. From his experience, Bob suggested that SSO and other noise effects on the signal line were handled quite well by IBIS. However, noise and SSO on ground and power rails was handled poorly by IBIS. Some mentioned that the DesignCon West 2004 summit featured presentations praising IBIS's ability to predict SSO. Participants agreed that simulation tool assumptions about crowbar currents make the difference between accurate and inaccurate SSO prediction. V-t tables in IBIS do not deterministically predict crowbar currents, as the power and ground rail currents are not simultaneously described. C. Kumar made this point in 1997 when proposing, in BIRD42, to add rail current data per buffer. Ian Dodd suggested that this data may not be usable by tools in its current form, especially since per-buffer rather than component-level data is included. Michael Mirmak added that per-buffer I-t behaviors are not directly measurable. Robert Haller noted that the intervals between parsers and specifications are increasing. He also noted that ICM and IBIS 4.1 may not become widely supported He wanted to know if the Open Forum could help reduce that delay and further encourage new feature adoption. Michael Mirmak responded by saying that some companies, though very few, take steps to provide "early adoption" models for new technologies, even if tool support does not currently exist for the features. The parser and specification delays are being addressed by the proposed roadmap, to reduce the time needed to get new features to tool vendors for inclusion in their tool updates. Mike LaBonte suggested that a user poll be issued by the Open Forum. This poll would ask users to prioritize their need for new features, as expressed in recent BIRDs, specification updates and new specifications. In addition, it would discover how familiar the user community is with the new technologies developed by the Open Forum. Finally, the poll could also inquire as to the timeframe needed by users for new feature rollout. Todd Westerhoff reiterated his concern about adequate support for existing keywords under current tools. Most advanced features are used by a very small group within the industry, with only five semiconductor vendors with a strong familiarity with proper IBIS generation techniques. Norio Matsui inquired about ICM applications on behalf of JEITA. While ICM is intended for interconnects, there is interest from passive component vendors in using ICM or a similar structure to describe their products (for example, EMI filters). Additionally, designers may wish to model packages with damping resistors and capacitors featured as discrete components. Does either ICM or IBIS 4.1 support these methods? Michael Mirmak responded that IBIS 4.1 can definitely include Berkeley SPICE netlists for such components, though tools may not easily use [External Circuit]s which feature passive-only netlists. ICM can model any passive structure using S-parameters in the frequency domain, which should be appropriate for Dr. Matsui's applications. Dr. Matsui also referred to ICEM EMC models, suggesting that integrating such model structures with IBIS and/or ICM may be desired by the industry. CONCLUDING ITEMS Michael Mirmak again thanked the presenters, supporters and sponsors for their help and support in making the Summit a success. After reminding the participants regarding the next Open Forum teleconference, Michael closed the IBIS Summit Meeting. NEXT MEETING The next Open Forum teleconference has been scheduled for April 23, 2004 from 8:00 AM to 10:00 AM US Pacific Daylight Time. ======================================================================== NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046 michael.mirmak@intel.com Senior Analog Engineer, Intel Corporation M/S FM6-45 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 788-4289 lgreen22@mindspring.com Green Streak Programs 20130 181st PL NE Woodinville, WA 89077 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 1-711 Boise, ID 83707-0006 LIBRARIAN: Roy Leventhal (847) 590-9398 roy.leventhal@ieee.org Consultant, Leventhal Design and Communications 1924 North Burke Drive Arlington Heights, Illinois 60004 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008 John_angulo@mentor.com Development Engineer, Mentor Graphics 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. 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Job posting information is not permitted. ibis-bug@eda.org To report ibischk3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibis_bugs/bugform.txt along with reported bugs. icm-bug@eda.org To report icmchk1 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/icm_bugs/icm_bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt and /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants and actual IBIS models are available on the IBIS Home page: http://www.eigroup.org/ibis/ibis.htm Check the IBIS file directory on eda.org for more information on previous discussions and results: http://www.eda.org/pub/ibis/directory.html * Other trademarks, brands and names are the property of their respective owners.