DATE: 03/22/05 SUBJECT: March 11, 2005 EIA IBIS Open Forum European Summit Minutes VOTING MEMBERS AND 2005 PARTICIPANTS Actel (Prabhu Mohan) Agere (Nirav Patel) AMD (Wasim Ullah) Ansoft Corporation Michael Brenneman Applied Simulation Technology Norio Matsui Cadence Design Systems Lance Wang, Donald Telian, Heiko Dudek* Cisco Systems Syed Huq, Mike LaBonte, Todd Westerhoff, Zhiping Yang, Vinu Armumugham, Salman Jiva, Satish Pratapneni, Il-young Park, Sergio Camerlo, Phillipe Sochoux, Eddie Wu, Gurpreet Hundal, Jayanthi Natarajan Fluent (Chetan Desai) Freescale (Jon Burnett) Hitachi ULSI Systems Kazuyoshi Shoji* Huawei (Jiang Xiang Zhong) IBM (Wesley Martin) Integrated Circuit Systems (ICS) (Dan Clementi) Intel Corporation Michael Mirmak, Arpad Muranyi* LSI Logic Frank Gasparik Mentor Graphics John Angulo, Guy de Burgh, Ian Dodd, Steven McKinney, Kim Owen, Stephane Rousseau* Micron Technology Randy Wolff, Paul Gregory NEC Electronics Corporation Takeshi Watanabe, Lori Askew, Takuno Tsuikana Panasonic Atsuji Ito Samtec Otto Bennig Siemens AG Eckhard Lenski*, Katja Koller*, Manfred Maurer*, Heinz Ibowski*, Wolfgang Rohmer*, Klaus Huebner* Michael Kindij* Signal Integrity Software Robert Haller, Douglas Burns, Barry Katz, Mike Mayer Sigrity Sam Chitwood, Jing Ting, Raymond Chen, Jiaguan Fang*, Teo Yatman* Silego (Joe Froniewski) Silicon Image (Ook Kim) Synopsys (Warren Wong) Teraspeed Consulting Group Bob Ross, Scott McMorrow, Tom Dagostino Texas Instruments (Jean Claude Perrin) Xilinx Ray Anderson, Sanjay Mehta Zuken Michael Schaeder*, Ralf Bruening* OTHER PARTICIPANTS IN 2005: Altera Khalid Ansari Bayside Design Kevin Roselle CelsioniX Kellee Crisafulli EMC Brian Arsenault, Daniel Nilsson, Jason Pritchard, Jinhua Chen EMF Consulting Ekkehard Miersch*, Simon Kunz* Enterasys Networks Fabrizio Zanella EPFL Alain Vachoux* Fujitsu Siemens Computers Martin Ramme* GEIA (Chris Denham) Green Streak Programs Lynne Green Infineon Technologies AG Thomas Steinecke*, Minea Gospodinova*, Amir Motamedi*, Yann Zinsius*, Christian Sporrer*, Radovan Vuletic* INSA Toulouse Etienne Sicard KAW Kazuhiko Kusunoki Leventhal Design Roy Leventhal Marvell Itzik Peleg* NetLogic Eric Hsu North Carolina State Univ. Ambrish Varma Politecnio di Torino Igor Stievano* Silicon Bandwidth Kim Helliwell Sun Microsystems Gustavo Blando Time Domain Analysis Systems Dima Smolyansky, Steve Corey Western Digital Mohammad Ali Independent Bernhard Unger (Siemens retired)* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode March 24, 2005 JEITA-IBIS Meeting - No bridge April 1, 2005 1-916-356-2663 1 350-5998 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- INTRODUCTIONS AND MEETING QUORUM The European IBIS Summit Meeting was held all day at the ICM conference center in Munich, Germany. About 28 people from 11 companies and institutes attended. The notes below capture some of the meeting content and discussions. The meeting presentations and other material are uploaded at: http://www.eda.org/pub/ibis/summits/mar05/ Ralf Bruening opened the meeting. Everyone agreed to skip the introductions to save time and move on to the full agenda. EDA vendors, model users, and semiconductor groups were all well represented. Ralf thanked the co-sponsors Mentor Graphics, Siemens, Cadence/FlowCad, and Zuken for sharing the meeting expenses. PRESENTATIONS AND DISCUSSION TOPICS The rest of the meeting consisted of presentations and discussions. These notes capture some of the content and discussions. More details are in in the uploaded documents. SIEMENS IBIS GROUP Eckhard Lenski, Siemens AG, Germany Eckhard reported that in many Siemens divisions, the use of analysis tools for SI, Xtalk, EMI, etc., is increasing. A group was founded within Siemens named SIG, Siemens IBIS Group. The reasons are to raise up a common quality standard for IBIS models, to save time by not checking the models twice, and to have an exchange of experiences and knowledge of the tools, the models, and the vendors. Siemens is starting to use the quality checklist as one part of incoming model inspection. Furthermore, the group has set up a list of common requirements concerning the process of model requests and model treatment. Another point is the necessity of some IBIS keywords and parameters that are needed by Siemens, but are only optional within IBIS, like overshoot, waveforms and package models. CAN WE STOP THE GROWING DISPARITY BETWEEN THE POTENTIAL OF IBIS MODEL PARAMETERS AND THE REALITY OF DELIVERED MODEL PARAMETERS? Eckhard Lenski, Siemens AG, Germany Eckhard introduced the presentation by stating that delivered IBIS models are not keeping up with the growing possibilities to model I/O behavior. He showed where delivered conditions for process, voltage and temperature (PVT) are less than or different than the Vcc and temperatures needed for the application. He illustrated where errors occurred on propagation delay, overshoot, and first wave switching when the extended range models were used. This forces unnecessary, overly conservative design changes. Eckhard provided a brief update of the IBIS Quality Committee documents, including the checklist, and stated that most of the work is done. He then compared IBIS keyword and subparameter extensions with what vendors are actually supporting. Eckhard commented on the ICM specification and indicated that it documents a fixed format for package and connector data, and that it might become a standard. He also mentioned the new Cookbook release and noted where some of the new items are being covered. The ICEM proposal already has a Cookbook. The upcoming BIRD95 is being processed, but more information is needed on how to extract the data. MODIFYING IBIS FILES Katja Koller, Siemens AG, Germany Katja was motivated by the observation that models were not good enough or were not available. She covered some examples including C_comp and clamp I-V table interactions with signal behavior. Also, she presented her investigations based on examining different vendor min-max models to come up with some correlations and scaling factors from typical data for process, voltage and temperature variations. Scaling for dynamic data is different and may be less accurate. While her tolerances were loose and up to 50%, it was a start toward improvement. Katja described some options to create a model when it was not available. For example, a missing 4 mA driver can be created from data derived from another 4 mA model from another vendor or from a model from the same vendor with either another technology or with similar technology. Furthermore, she indicated in a table some factors that can lead to worst case conditions for some measured parameters (overshoot, timing, crosstalk, and EMI). In the subsequent discussion, someone suggested that a vendor could supply the scaling factors. However there was concern that even that information gave away process yield information. AN INITIAL CASE STUDY FOR BIRD95: ENHANCING IBIS FOR SSO POWER INTEGRITY SIMULATION Sam Chitwood, Raymond Chen, and Jiayuan Fang, Sigrity, Inc. USA Jiayuan Fang introduced the presentation, also given at the IBIS Summit Meeting, January 31, 2005. Jiayuan presented a study for BIRD95, mentioning that up to today, IBIS could not be used for power fluctuation calculations. He made simulations with an ideal power supply and simulations which showed that the current flowing through the power supply is not modeled correctly by just using IBIS models. So, there is no information about the pre-driver current and little information about the crowbar current in today’s IBIS models. He showed that with the use of BIRD95 there is a possibility to fix this problem. BIRD95 recommends three parasitic current extractions. He pointed out that the pre-driver current is independent from the load conditions, but that the crowbar current is load dependent. The last part is the current through a non-ideal power supply, which depends on the package parasitics. The new results with an improved IBIS model according to BIRD95 showed a good correlation with spice. He pointed out excellent correlation with the voltage waveform spikes coming from pre-driver current. Small differences might still come from unmodeled gate modulation effects. He concluded by mentioning that more investigation is necessary for other technologies like SSTL, ECL, etc. Christian Sporrer pointed out that the power distribution system of the whole IC should be used for getting even more accurate results. IBIS IN THE DESIGN CHAIN OF NOISE MODELING Manfred Maurer, Siemens AG, and Thomas Steinecke, Infineon Technology AG, Germany For automotive customers, Thomas Steinecke explained that along with signal integrity, the power integrity and emission compliance are very important. He gave an overview of how the IBIS I/O circuit model and the power net model (ICEM) fit together well in IBIS 4.1. Simulation is needed to validate EMI compliance. For reliability, Thomas pointed out that a top-down approach is taken from the car system to the PCBs to the ICs. But, noise source modeling is done from the bottom up. Good models are needed for the ICs. Then, the coupling paths are modeled as part of the PCB analysis to show the conducted and radiated noise for the whole (car) system. For modeling, Thomas showed that the IC can be divided into different functional blocks, and each block is modeled by equivalent current sources (ECS). Many of these ECS build up the chip emission model, which together with the package parasitics build the ICEM model. He showed two ways an ICEM model could be included in IBIS 4.1. These were by using I-t tables, or by using an executable SPICE model. Manfred Maurer then continued on and explained in more detail how this could be achieved. The two current sources can be modeled either by a piece-wise linear (PWL) table or with an actual SPICE subcircuit. He then provided an overview demonstrating how the ICEM, IBIS, and BIRD95.1 and BIRD97 proposals can work together to get better simulation results. In the discussion that followed, it was noted that the noise in the core is code dependent. Therefore a statistical approach is taken instead of actual pattern simulation to get this noise. Also discussed was whether PWL or mathematical methods were faster, and that PWL features were available in VHDL-AMS, but not Berkeley SPICE. THE ROLE OF IBIS IN NEAR-FIELD EMISSION PREDICTION OF ICS Etienne Sicard and Alexandre Boyer, National Institute of Applied Science (INSA), France; and Gilles Peres, EADS Airbus Industries, France To introduce the critical need for electromagnetic compatibility of integrated circuits, Etienne explained that, in a car, the microcontroller unit may interfere with the mobile phones, the automobile computer, and the brake system. Even the airbag could misfire. Therefore, it is important to simulate Electromagnetic emission before fabrication. He pointed to a free program downloadable from their IC-EMC website: http://www.ic-emc.org/ It uses mostly the package parasitics from an IBIS model in conjunction with the ICEM model and (free) WinSPICE for time-domain simulation. A Fourier transform converts the currents to get the current dipole magnetic field. The most important components are Hx and Hy. Less important are Hz and the electric field components Ex, Ey, and Ez. Huge currents (greater than 1 A) flowing inside the IC contribute to the magnetic field components. The program uses specially defined comment characters to bring the ICEM parameters into the IBIS file. He showed excellent correlation between simulation and measured results considering that comparisons within about 10 dB are considered good for EMC. The test chip contained six different cores (with one of them very noisy) constructed with bad design rules. Another chip with good design rules and layout was used for reference. Both simulation and measurement showed the same EMI noise locations and magnitudes. In the discussion that followed, Etienne responded to a question that at this time, package radiation is not examined, and that most of the radiation came from the core. This method of calculating EMI might also be used for small boards. COMPUTER-ASSISTED MODELING OF DIGITAL I/O BUFFERS FOR IBIS Flavio Canavero, Ivan Maio, and Igor Stievano, Politecnico diTorino, Italy; Madhavan Swaminathan, Georgia Institute of Technology, USA; and Paul Franzon, North Carolina State University, USA Igor presented required goals of I/O buffer macromodeling as discussed by the IEEE/CMPT TC-12 sub-committee. He cited IP protection, a vendor independent format, and easily automated generation from SPICE or measured data as most important. With black-box models, Igor stated that even difficult drivers such as DDR memories and LVDS technology with pre-emphasis have been successfully modeled. This black-box approach is based on mathematical equations, and the resulting model would work well within the IBIS Version 4.1 language extensions and various flavors of SPICE. The tool M(pi)log (macromodeling via parametric identification (pi) of logic gates) is available by request. Igor illustrated the generation steps. These include setting up the simulation decks, running the simulations, and then using the tool to process the results to create a model according to some selected parameters. Even the [External Model] format in VHDL-AMS is supported. In the discussion that followed, Igor indicated that different classes of stimuli for test deck generation are used for different types of devices (such as for CMOS, pre-emphasis, or CML buffers). The process could also help close the gap for some needed IBIS features Eckhard Lenski discussed earlier for electrical simulation of the more complex buffers. LUNCH/DISCUSSION (30 Minutes) The group recessed for a brief working lunch. CONSIDERATIONS ON SWITCHING CHARACTERISTICS Michael Schaeder, Zuken, Germany Michael introduced some general considerations about three problem areas in IBIS models. He listed extremely long trailing data (not contributing to the switching area description), overclocking, and special behavior such as pre-emphasis. He showed simulation changes based on trailing data removal. Also short periods can create overclocking simulation errors because the tool has to determine how to change between High and Low states for unfinished transitions. The tool still needs to find a continuous output impedance for better results. Michael also illustrated the possibility of modeling a high-speed differential ECL driver with programmable pre-emphasis as a single stage buffer. He questioned whether it was valid and showed some results. But test pattern variations and the amount of pre-emphasis would probably be factors with this type of approach. Michael concluded by noting that long trailing data, overclocking and pre-emphasis all influence simulation result accuracy. PRE/DE-EMPHASIS BUFFER MODELING WITH IBIS Arpad Muranyi, Intel Corporation, USA Arpad presented different ways to model pre-/de-emphasis buffers in IBIS. These included independent, manually wired, OR building blocks, [Driver Schedule] coding, and *-AMS extensions in IBIS Version 4.1. He gave a short review of the pre-emphasis structures based on one main and one delayed-by- one-bit, inverted boost buffer connection. Including C_comp effects is difficult, because the C_comp loading effects of the main buffer need to be compensated for in the boost buffer. Arpad showed simulation differences between SPICE and IBIS if this is not taken into account. The problem can be solved by using separate V-T tables for the transition edge combinations of strong-to-strong, strong-to-weak, and weak-to-strong. One way of implementing this is to use a state machine which can be described in VHDL-AMS. Arpad showed some very good matching results based on this approach. He even considered some approaches to modeling asymmetrical buffers. He also showed some discontinuities associated with unfinished edges (which were not addressed by the approach). Overall, the method shortened the simulation time by a 2.5 factor over a more conventional switching approach. Arpad concluded by listing some next steps to improve the algorithm. IBIS MODELS; THE FIRST STEP TOWARDS HIGH SPEED DESIGN KITS Stephane Rousseau, Mentor Graphics, France Stephane historically reviewed technology evolution. Starting with the 1980s, relatively slow TTL technologies had almost no signal integrity (SI) problems. With speed increases in the 1990s, vendors started issuing SPICE models. They were complex and simulations were slow. IBIS emerged as a faster, simpler, and standard solution in 1993. With serial Gigabit I/Os, vendors began switching back to SPICE and encrypted SPICE models, slowing down simulations. IBIS Version 4.1 emerged as a way to wrap IBIS around SPICE or VHDL-AMS which was faster and did not reveal the internal intellectual property (IP) content. Stephane showed the advantages of each block and certain combinations and how they can be combined within an IBIS multi-lingual wrapper. With these blocks, other blocks and stimulus patterns can be configured into design kits also containing reference designs, constraint rules, footprints, and so forth. Stephan showed some tools for generating stimulus patterns and configuring the buffers. He predicted more future design kits and more enhancements. He also showed how this approach benefits semiconductor/FPGA vendors, EDA vendors, and customers. Stephane closed by asking whether the IBIS Committee should drive for high speed design kit requirements and propose a common format with common content. During the discussion, someone suggested that Stephane should start a survey or raise the question on the IBIS or SI-reflectors regarding interest in such design kits. One concern was that with on-going changes such as die shrinkage, vendors might have to update the kits about every six months. Even new IBIS models might not be available. Stephane noted that vendors already have to support these and other changes as well. Creating a new design kit is not a problem. Stephane closed by stating that design kits help customers, because they can get simulations to run with just the push of a button. MODELLING COMPLEX IO WITH IBIS 4.1 Don Telian, Cadence Design Systems, USA Heiko Dudek, Cadence Design Systems Heiko gave the presentation. This presentation was also given at the IBIS Summit Meeting on January 31, 2005. Heiko showed that IBIS started around the PCI-chipset and a Pentium microprocessor. Since that time, the models got more and more complex, and some IO models didn’t fit inside the IBIS-box anymore. So, there is a necessity to widen the box, and he questioned how to do so. To solve this, Donald Telian conducted some web surveys in 2003 and 2004. According to the results, HSPICE is increasingly being used for models outside of the box, but customers do not want this as a longer term solution. One alternative is to use *-AMS models for true behavioral implementations. Intellectual property (IP) protection might become an issue according to customers, and many are unfamiliar with AMS. Another approach for the shorter term is to consider using SPICE directly for macro-model generation. Heiko reported that he used this approach with a basic IBIS Version 2.1 block and built macro-model extensions around it to support IBIS advances. The IBIS Version 4.1 approach can support this. But, Berkeley SPICE is too limited and does not support parameters or an IBIS block and other critical elements. So, he proposed some small extensions beyond Berkeley SPICE to enable macro-modeling solutions as a method to quickly add complex I/O modeling capability. Heiko clarified in response to a question that IBIS additions meant syntax changes are owned by the IBIS committee and processed very slowly with new BIRDs. The model developer has to wait for this process to be completed, whereas with macro-modeling, the model developer can configure advanced features more quickly and when needed. CLOSING TOPICS Ralf Bruening thanked the participants for attending and the presenters for the excellent presentations. Ralf also thanked the sponsors for keeping the European IBIS Summit Meeting active. Much interaction existed during the breaks, and Ralf viewed this as one of our most successful Summits. NEXT MEETING The JEITA IBIS Event will be held March 24, 2005 in Japan. No telephone bridge is available. The next IBIS Open Forum teleconference will be held April 1, 2005 from 8:00 AM to 10:00 AM US Pacific Time. The meeting will be chaired by Syed Huq. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046 michael.mirmak@intel.com Senior Analog Engineer, Intel Corporation FM6-45 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 1-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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