DATE: 02/15/06 SUBJECT: February 9, 2006 EIA IBIS Open Forum Summit Minutes VOTING MEMBERS AND 2006 PARTICIPANTS Actel (Prabhu Mohan) Agere (Nirav Patel) AMD (Wasim Ullah), Tadashi Arai* Ansoft Corporation Michael Brenneman* Applied Simulation Technology Fred Balistreri* Cadence Design Systems Lance Wang* Cisco Systems Syed Huq*, Mike Labonte AbdulRahman Rafiq*, Pedo Miran* Salman Jiva*, Gurpreet Hundal* Todd Westerhoff* Fluent (Chetan Desai) Freescale (Jon Burnett) Green Streak Programs (Lynne Green) Hitachi ULSI Systems Kazuyoshi Shoji* Huawei Technologies (Xiangzhong Jiang) Integrated Circuit Systems (ICS) (Dan Clementi) Intel Corporation Michael Mirmak*, Arpad Muranyi*, Stephen Peters, Vishram Pandit* LSI Logic (Frank Gasparik), Kim Helliwell* Praveen Soora* Marvell (Itzik Peleg) Mentor Graphics John Angulo*, Ian Dodd*, Gary Pratt* Micron Technology Randy Wolff* NEC Electronics Corporation (Takeshi Watanabe) Panasonic (Atsuji Ito) Samtec (Corey Kimble) Siemens AG Eckhard Lenski, Manfred Maurer* Siemens Medical David Lieby* Signal Integrity Software Barry Katz*, Douglas Burns*, Mike Mayer* Walter Katz* Sigrity Sam Chitwood* Silego (Joe Froniewski) Silicon Image (Ook Kim) STMicroelectronics (Antonio Girardi) Synopsys Andy Tai*, Ted Mido* Teraspeed Consulting Group Bob Ross* Texas Instruments Otis Gorley, Richard Ward* Xilinx (Ray Anderson) Zuken (Michael Schaeder) OTHER PARTICIPANTS IN 2006: Agilent Sanjeev Gupta* Altera Khalid Ansari* Amkor Technology Nozad Karim* Apple Computer Zhiping Yang* Dell Aubrey Sparkman Force10 Networks Robert Badal* GEIA (Chris Denham) Rambus Nirmal Jain* Samsung Heeseok Lee* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode February 17, 2006 1-916-356-2663 2 404-6553 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- INTRODUCTIONS AND MEETING QUORUM Michael Mirmak opened the meeting by thanking the co-sponsors: Cisco for providing the lunch and refreshments, Applied Simulation Technology for help with registration and logistics and Mentor Graphics for help on the display booth. Michael called for individual introductions of the participants. 38 people from 23 organizations people were in attendance. A cross-section of IBIS users, IBIS model makers and EDA tool vendors were represented. IBIS CHAIR'S REPORT AND ROADMAP UPDATE Michael Mirmak, Intel Corp. Michael Mirmak noted recent events including the ICM 1.1 standardization and the success of the Asian IBIS Summit. Membership in 2005 was 32 members. At least two new members are expected in 2006. Three ICM parser licenses were issued. 2005 was a break even year for financials. IBIS 4.2 approval and release is planned in the short term, followed by the IBIS 4.2 parser. Other short term plans include completing remaining IBIS 5.0 BIRDs and working on an ICM 1.1 Cookbook. Michael showed a list of BIRDs for inclusion in IBIS 4.2 versus 5.0. Michael stressed that IBIS 4.2 is for standardization of IBIS and AMS whereas IBIS 5.0 will be a complete SI modeling solution. HDL AND IBIS 4.1 MODELS IN A FUNCTIONAL DDR MEMORY INTERFACE ANALYSIS Randy Wolff, Micron Technology Randy Wolff stated that this was a collaborative project between Micron and Gary Pratt of Mentor Graphics. The project was to analyze a complete DDR memory interface in one simulation. Using IBIS 4.1, HDL functional models and IBIS I/O models were combined. The HDL code took care of timing checks and the IBIS models contained the basic electrical checks. The HDL models were used to control the simulation, where a random address and data pattern generator provided the stimulus pattern for a Write cycle, and the memory responded with a corresponding Read cycle. Timing checks in the HDL code as well as digital and analog waveform outputs from the simulation were shown. Randy mentioned future enhancement planned for the project including adding a slew-dependant timing calculation into the HDL code, modeling a DDR2 system and adding a full S-parameter model for the PCB to enhance crosstalk simulation. Randy stated the desire to see two IBIS enhancements: the ability to instantiate a [Model] in a [Circuit Call] statement and corner-specific Parameters passing. IBIS: ADDRESSING CHALLENGES IN BEHAVIOR AND MEASUREMENT Ian Dodd, Mentor Graphics Corporation Ian Dodd stressed the large need for a new lowest common denominator in modeling. This was available with legacy IBIS models, but not currently with AMS language models. He noted applications where IBIS 3.2 is not adequate. He went over synchronous timing analysis and noted that this was the predominant technology when IBIS 2.1 was developed. He then talked about source synchronous timing analysis and noted how this was the common technology when IBIS 3.2 was developed. He detailed new issues affecting IBIS and focused specifically on DDR2 technology. He mentioned that he did not want to hard code DDR2 specific features into the waveform analysis or results spreadsheets. Ian proposed enhanced behavior and measurement information in IBIS models, detailing several options. A first option was using transistor level SPICE models. A second option was using macro models. Third, he detailed use of analog-only AMS as a stepping stone to full AMS. The fourth option highlighted was use of full AMS. He concluded that there will only be a lowest common denominator if all major EDA vendors agree on a single solution and add it to their SI tools. Todd Westerhoff initiated some discussion on the need to address AMS in terms of what it really is: VHDL-AMS or Verilog-AMS, and simulators should specify support for one or both, but not just AMS. C_COMP AND BUFFER SCALING OBSERVATIONS Bob Ross, Teraspeed Consulting Group Bob Ross began by showing a full IBIS 2.1 buffer where C_comp is part of the buffer. He mentioned that the typical buffer model mentioned only R_fixture, V_fixture and C_comp with no mention of L and C components in the DUT and fixture parameters. In the case where C_dut and C_fixture are needed to describe parasitics in the measurement, these capacitances could be added to C_comp. Bob talked about modeling a 2-tap pre-emphasis differential buffer. In this example, the definition of C_comp is complicated. One solution is to have C_comp as a load. The other is using C_comp as a buffer element in a macro model. Bob proposed using and tweaking C_fixture values for a 2-tap pre-emphasis buffer. Michael Mirmak asked if Bob was suggesting continued use of [Driver Schedule] for modeling of pre-emphasis and multi-tap buffers. Bob replied yes. CURRENT STATUS - IBIS 4.1 MACRO LIBRARY FOR SIMULATOR INDEPENDENT MODELING Todd Westerhoff, Cisco Systems, Inc. Todd Westerhoff gave an overview of the history of the IBIS macro model library. He mentioned that SPICE use is steadily increasing. IBIS 4.1 supports AMS, but adoption has been slow. Macro modeling was proposed as an alternative to full AMS a year ago by Donald Telian. He showed the current support of Verilog-A(MS), Verilog-AMS, and VHDL-AMS in 12 popular SI tools. The goal was to support advanced modeling across all the tools. Macro models instantiate blocks with pre-defined functions and behaviors. The blocks are parameterized by passing values into the elements. Blocks are interconnected, and external ports to the model are defined. The IBIS macro concept is a library of AMS elements modeled after sources and elements found in popular SPICE tools. Currently, a preliminary library is in place, and the committee is recruiting semiconductor vendors to test the library. Recent activities include final coding and testing of the library, acceptance of BIRD100.2, recruiting Paul Fernando of NCSU to help with model translation issues and releasing library versions in Verilog-A(MS) and VHDL-A(MS). Significant compatibility issues with AMS implementations in different EDA tools have been identified. Todd highlighted the need to perhaps document the AMS language subsets that are required. Next steps include driving language support and creating additional templates if desired. INTRODUCTION TO THE IBIS MACRO MODEL LIBRARY Arpad Muranyi, Intel Corporation Arpad Muranyi recapped the IBIS macro modeling concept. He listed the contents of the library including resistors, capacitors, inductors, voltage and current sources, an ideal t-line and eight IBIS buffers. Arpad detailed the library's test suite including the parameter data file format and the architecture. He then showed the file systems for the Verilog-A(MS) distribution for HSPICE and the VHDL-A(MS) distribution for SMASH. An example of a resistor was then shown including simulation code, library code and simulation waveform results. Examples were then shown of a Voltage-controlled capacitor, an IBIS I/O buffer and a pre-emphasis buffer. Arpad showed a quick demonstration of using the IBIS-to-macro model Conversion tool. DISCUSSION - MACRO MODELING AND LANGUAGE MODELING Some discussion ensued on how to control the library in terms of who is allowed to update the library and how this activity is checked for validity. ASIAN IBIS SUMMIT SLIDE SHOW Syed Huq, Cisco Systems, Inc. Syed Huq showed several pictures of the Asian IBIS Summit and solicited comments from other participants. ASIAN IBIS SUMMIT REVIEW Bob Ross, Teraspeed Consulting Group Bob Ross presented an overview of the Summit meeting. There were about 160-180 people in attendance. The full schedule included 13 presentation topics and three introductory speeches. There were many major successes as well as some minor difficulties. Feedback questionnaires were handed out, and 102 were turned in. Results showed overwhelming meeting support and IBIS familiarity. Also, few people from China subscribe to the email reflectors. There was a good balance of presentations that covered a wide variety of topics. Bob then mentioned future Asian Summit plans including potential summits in Japan and potentially a DesignCon Summit in 2007. SSO SIMULATION WITH IBIS Manfred Maurer, Siemens AG. Manfred Maurer stated that SSO simulation is very important when analyzing systems. He detailed his simulation setup including a quiet output and a switching output. He demonstrated creation of a voltage controlled current source (VCCS) for modulating the output of the pullup and pulldown transistors. He highlighted modeling differences between his VCCS models in 2000 versus present day. Additional multiplier coefficients were extracted for rising and falling edge characteristics. The VCCS model with the additional coefficients did not correlate well with the HSPICE model. Manfred summarized differences in buffer characteristics between buffers seen in the year 2000 versus 2006. He then highlighted an enhanced VCCS- behavioral model with a static coefficient and the addition of a dynamic coefficient. The dynamic coefficient is extracted for a known inductance in the power supply. There were still differences between the improved model and the transistor level model. He summarized that the SSO could be simulated with much better correlation from IBIS to the transistor model with table information provided by BIRD95 and BIRD97. DIFFERENTIAL SYSTEM DESIGN AND POWER DELIVERY Vishram Pandit and Michael Mirmak, Intel Corporation Vishram Pandit stated that common assumptions for differential systems are not valid for all differential drivers. Understanding current behavior is key to proper differential power delivery design. He showed the three types of differential drivers - full, half and pseudo differential. Half differential systems were analyzed in detail. Four termination schemes for half differential drivers were shown. Currents in power and ground were analyzed for each termination scheme. For half differential drivers, it was shown that the currents in the lines may or may not be equal and opposite. So, it is important to analyze the true current profile when determining the power delivery network design solution space. Vishram showed an example of computing different current profiles for power and ground and then comparing these to an IBIS model implementation. Questions were posed to the IBIS community about whether IBIS could model driver power on/off events, and would BIRD95 include all the data needed for this kind of analysis. PROPOSED TOUCHSTONE(R) IMPROVEMENTS FOR OPTIMIZATION OF MIXED PDS AND I/O MODELS Sam Chitwood, Sigrity Sam Chitwood highlighted reasons for using Touchstone(R) models to model power and ground structures that affect an I/O signal's performance. Three tips on Touchstone(R) models given were minimizing the number of ports whenever possible, having a proper frequency sweep for time domain simulations and using as dense of a linear sweep as possible for the high frequency region. He then went over limitations of the S model in SPICE. A curve fit approach was shown that is an alternative to SPICE's convolution-based S model. Benefits included large gains in simulation efficiency, equivalent circuit models that are compatible with all SPICE simulators with no limits on the number of supported ports and passivity issues can be eliminated during the conversion. Sam proposed supporting multiple reference impedances in the Touchstone(R) specification. A point stressed during questioning was that this technique would only apply to simulation data and never to measurement data. ACCURACY OF IBIS MODELS WITH REACTIVE LOADS Arpad Muranyi, Intel Corporation Email discussions on the reflector prompted Arpad Muranyi to compile data related to IBIS models driving capacitive loads. He showed how V-t curves are used as time variant scaling coefficients for the I-V curves to generate partially ON I-V curves during transitions. V-t curves are converted to K-t curves for use in the IBIS model algorithm. Arpad showed the equations for solving the pullup and pulldown scaling coefficients. He highlighted that none of the equations include dI/dt and dV/dt terms that would be needed to solve for reactive load effects. A big consideration in the effect of the reactive load is the time constant of the reactive load versus the switching frequency of the model. He encouraged implementation of better algorithms in tools if needed or developing a solution with AMS modeling. OPENS/DISCUSSIONS A discussion was opened up about whether or not to lock down the macro model library. Walter Katz felt that it would be a bad idea to not open up the library, as users should be able to add building blocks to model new technologies that can't be modeled with the available primitives. Michael Mirmak posed the question of who was in support of standardizing the library. Arpad mentioned that standardizing a subset of the AMS languages that all tool vendors would support is a good idea. Todd Westerhoff stated that we shouldn't ask about standardization without more experience in creating real world models from the macro model library elements to determine if the library contains enough elements. We also need to define the problems that the simulators need to be able to solve. It was agreed that the standardization question should be re-examined once several new technologies such as Rocket I/O are modeled with the macro model library elements. Walter Katz brought up the issue of needing a way to tie receiver characterization data into an IBIS model. Perhaps this could be implemented through a keyword pointing to an [External Model], whereas currently the only method is through comments included in the model and parsed by the simulation tool. Richard Ward asked about ways to characterize an eye diagram when it exists in the middle of a chip, i.e. nowhere that can be measured. Walter Katz had some ideas on how to do this. Another discussion ensued about where to go in terms of modeling the core power on the chip. Sam Chitwood of Sigrity felt that this was a very important issue affecting the design of power distribution systems. At the conclusion of the ad-hoc discussion, Michael adjourned the meeting. NEXT MEETING The next IBIS Open Forum teleconference will be held February 17, 2006 from 8:00 AM to 10:00 AM US Pacific Time. A vote is scheduled for BIRD102. The next IBIS Summit will be held March 10, 2006 at DATE 2006. No telephone bridge is available. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-3788 michael.mirmak@intel.com Server Platform Technical Marketing Engineer, Intel Corporation FM5-79 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 01-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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