DATE: 11/10/06 SUBJECT: October 31, 2006 EIA IBIS Open Forum Summit Minutes GEIA BALLOT ELIGIBILITY (Must have attended 2 of the last 3 meetings, including Summits) Member GEIA Eligible (A = Active) -2 -1 Current Meeting ---------------------------------------------------------------- AMD X Cadence A X X X Cisco X Green Streak Programs X Intel A X X X Hitachi ULSI Systems X Mentor Graphics A X X X Micron Technology X NEC Electronics Corporation A X X Siemens AG X Signal Integrity Software A X X Sigrity X Synopsys X Teraspeed Consulting Group A X X X Toshiba X Texas Instruments X ZTE X VOTING MEMBERS AND 2006 PARTICIPANTS Agere (Nirav Patel) Agilent Sanjeev Gupta, Nilesh Kamdar AMD [Wasim Ullah], Tadashi Arai* Apache Design Solutions Ji Zheng Applied Simulation Technology Fred Balistreri Cadence Design Systems Lance Wang*, Lanbing Chen, Wenliang Dai, Jinbai Liu, John Peng, Coco Xu, Lily Yang, WenJian Zhang, Alex Zhao, Weiran Zhao, Zhangmin Zhong, George Zhou, Yanagi Akio*, Yukio Masuko*, Norikazu Takada* Cisco Systems Syed Huq, Mike LaBonte, AbdulRahman Rafiq, Pedo Miran, Salman Jiva, Gurpreet Hundal, Todd Westerhoff Fluent (Chetan Desai) Freescale (Jon Burnett) Green Streak Programs Lynne Green Hitachi ULSI Systems Kazuyoshi Shoji*, Matsuo Kouji* Integrated Circuit Systems (ICS) (Dan Clementi) Intel Corporation Michael Mirmak*, Arpad Muranyi, Stephen Peters, Vishram Pandit, Junyong Deng, Haifeng Gong, Guobing Han, Tao Hu, Karen Kang, Kuen Yew Lam, Fanghui Li, Dan Liu, Albert Mu, Zefeng Ni, Jirong Wang, Mingchang Wang, Even Wu, Fan Xia, Baoshu Xu, Jiannan Xu, Long Yang, Maoxin Yin, Xiangyin Zeng, Kevin Zhang, Xinjun Zhang, Zheli Zhang LSI Logic Frank Gasparik, Kim Helliwell, Praveen Soora Mentor Graphics John Angulo, Ian Dodd, Gary Pratt, John Shields, Simon Vines, [Guy de Burgh], Simon Hou, Baolong Li, Nan Liao, Xuefeng Liu, Yan Liu, Vivian Pan, Danny Perng, Haolei Zhu, Minoru Ishikawa*, Kenji Kushima* Micron Technology Randy Wolff NEC Electronics Corporation Takeshi Watanabe*, Kontaro Hachiya*, Saito Toshiyule*, Itsuki Yamada* Samtec (Corey Kimble) Siemens AG Eckhard Lenski, Manfred Maurer, Katja Koller, Klaus Huebner, Heinz-Hartmut Ibowski, Flavio Maggioni, Roberto Preatoni Siemens Medical [David Lieby] Signal Integrity Software Barry Katz*, Douglas Burns, Mike Mayer Walter Katz, Kevin Fisher Sigrity Sam Chitwood, Raymond Chen, Xianfeng Li, Jack Lin, Jing Wang Silego (Joe Froniewski) STMicroelectronics (Antonio Girardi) Synopsys Andy Tai, Ted Mido, Xuefeng Chen, Jinghua Huang, Yan Luo, ChangLei Zhang, Qin Zhang Teraspeed Consulting Group Bob Ross* Texas Instruments Otis Gorley, Richard Ward Toshiba Yasumasa Kondo*, Yoshishiro Hamaji Motochika Okano Xilinx (Ray Anderson) ZTE Shunlin Zhu, Bin Chen, Huifeng Chen, SonGrui Chen, Xiaolin Chen, Hui Jiang, Gu Li, Fuming Wu, Lixian Yang, Xiang Yao Zuken Michael Schaeder, Ralf Bruening OTHER PARTICIPANTS IN 2006: Acro Information Technology Jimmy Zhong Actel (Prabhu Mohan), Ann Lau Altera Khalid Ansari, David Lieby Amkor Technology Nozad Karim Ansoft Corporation Michael Brenneman, Andy Byers, Song Deng, Jack Qui, Sally Wang Apple Computer [Zhiping Yang] Ashenden Designs Peter Ashenden ATE Service Corporation Yutaka Honda* ATP Electronics Dan Li, Charlie Liu Atmel Corporation Pucheng Li Beijing Institute of Technology Kun Deng Betty TV Stephanie Goedecke Bosch Ingo Doerr, Jurgen Hasch Buffalo (Melco Holdings) Kazuyoshi Tsukada* Canon Seiji Hayashi*, Sou Hoshi*, Shoji Matsumoto*, Tatsuo Nishino* Celestica Harrison Xue, Jiang Zhu China Integrated Circuit Shirley Hu Centec Networks, Inc. Lifeng Qin, Kai Zhao CSIC Yongning Zai Cybernet Systems (KAW) Kazuhiko Kusunoki*, Azusa Harada Toshiyo Saito, Keiji Soyama, Ady Deng, David Ding, Summer Li, Golden Qian, David Xu, Masahito Kobayashi* Datang Mobile Communications Baisun Chen, Jianchao Zhao Equipment Dell Aubrey Sparkman East China Institute of Jian Pan Computing Technology Eastern China Institute of Wen Dai, Han Liao Engineering EDN China Changli Ying, Gang Yao EETimes Japan Norihiro Satsukawa* EFM Ekkehard Miersch Fiberhome Telecommunications Qi Zheng, Jianchun Wan Technology Foctel Jianchun Wan Force10 Networks Robert Badal Free Electron Software Al Davis Fujitsu Hikoyuki Kawata*, Toshiro Sato* GEIA (Chris Denham) Global Engineering Solutions Zhenning Liao*, Satake Matsuru* HiSilicon Technologies Song Jun Hong Jing Company Lia Song Hongsi Qunhui Yu Huawei Technologies Weidong Liu, Zhang Chen, Jin Hu, Chungxing Huang, Peng Huang, Gongxian Jia, Zhiwei Li, Qiang Lei, Yitong Wen, Liang Wu, Shengyu Wu, Huawei Yang, Zhoa Yi, Yun Zhu Huawei-3Com Technology Dingding Chen, Huanyang Chen, Zhongjian Chen, Xinnian Duan, Chunjiang Gu, Cheng Li, Xiaoqun Li, Fuqiang Shi, Guiwei Suo, Bo Wang, Wei Yang, Haitao Zhang, Wenhua Zhu, Yuan Zhuang IBM Lance Thompson, Narimasa Takahashi* Infineon Radovan Vuletic, Minka Gospodinova Christian Sporrer, Amir Motamedi Interactive Device Technology David Chen, Andy Li, Yuyang Wang, Liang Xu Inventec Corporation Zhong Peng, Xiaoping Yang, Yan Zhi IVIS Hiroyuki Mashima* Japan Aviation Electronics Hiroaki Ikeda* JEITA Atshushi Ishikawa Jiangsu Automatics Institute Boxing Deng Leventhal Design Roy Leventhal Lianchuang International Jason Wang Advertising (EE Times China) Lynguent Andrew Levy Marvell (Itzik Peleg) NXP Semiconductors Sudarshan Honnudike NCSU Paul Franzon Panasonic Atsuji Ito*, Kazuo Ogasawara* Philips Herve Menager Politecnico di Torino Igor Stievano Rambus Nirmal Jain RadiSys Corporation Yiming Cheng, Greg Fu, Guangcao Fu, Jeffrey Yang, Siyuan Yang Right Solution Industries Chao Chen, Rudy Shi Samsung Heeseok Lee, Il Seong Schneider Electric Gang Wu Shanghai Jade Technologies Dunear Huang, Howard Wang Shanghai JiaoTong University Bin Chen, Zhigang Hao, Shijie Huang, Feng Li, Tongyu Peng, Liu Wang Xuehong Yu, Kai Zhu Shanghai Municipal Information Jing Lin Commission Shanghai Silicon Intellectual Bulu Xu Property Exchange Sharp Yoshifumi Ohshima* SI Institute Chengfeng Weng Silicon Image (Ook Kim) SimLab Heiko Grubrich Sinosun Technology Cui Peng Tandem Consulting Jack Luo Trident Multimedia Technologies Evelyn Cao (Shanghai) Vectronix AG Luca Giacotto VeriSilicon Steven Guo, Zhan Zhou Via Technologies Jummy Hsu Winnet Electronics Wenhao Liang, Xin Xu, Xigu Technology Zhiyuan Chen In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode November 17, 2006 1-916-356-2663 3 676-3004 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- WELCOME AND INTRODUCTIONS The IBIS Open Forum Summit was held in Tokyo, Japan at the headquarters of JEITA (Japan Electronics and Information Technology Industries Association). About 38 people representing 52 organizations attended. The notes below capture some of the content and discussions. The meeting presentations and other documents are available at: http://www.eda-stds.org/summits/oct06b/ Takeshi Watanabe opened the Summit meeting by thanking the participants and recalling the successful JEITA-IBIS Joint Meeting of 2005. He observed the number of attendees and presentations, and predicted another successful event this year. Michael Mirmak made a few brief comments regarding the history and growth in IBIS, in particular the strong and long-standing relationship between IBIS and JEITA. He asked for the continued help and support of Japanese companies and engineers in advancing IBIS standard development. He concluded by thanking the primary sponsor JEITA for their support, plus the co-sponsors, ATE Service Corporation, Cadence Design Systems, Cybernet Systems, Mentor Graphics and Synopsys for their financial and logistical support. The regular presentations followed the conclusion of the introductory remarks. JEITA EDA-WG ACTIVITY Takeshi Watanabe, NEC Electronics Takeshi provided an overview of JEITA activities related to IBIS and EDA. JEITA's membership has interests in SI, EMI and PI (power integrity) in component types including ICs, RF modules, passive components, packages, oscillators, connectors, cables, PCBs and flexible PCBs. JEITA's major short-term interests include studies of interconnect models, creating models of passive components and interconnects, plus creating an IBIS-related modeling website. Bob Ross inquired whether the proposed JEITA IBIS portal website would be open to the public. Takeshi responded that it would be open, but that development may take some time. THE DIRECTION OF IBIS AS A STANDARD Michael Mirmak, Intel Corporation (USA) Michael began the formal agenda of presentations by summarizing the state of IBIS today and its history since version 2.1. He noted the steady growth of the specification in features, including the addition of support for the EBD format, Berkeley SPICE, the Verilog-AMS and VHDL-AMS languages and the proposed introduction of links to ICM and user- defined measurements. He briefly outlined the recent proposal to add an application programming interface (API) to IBIS, to support additional languages such as C, for advanced channel analysis. He concluded by calling upon the participants to register their opinions on the API through the IBIS Open Forum. Tadashi Arai inquired how many vendors are distributing models based on the *-AMS languages. Michael responded that he knew of at least one (Intel) and that he deferred to other model producers to speak for their own practices. Yasumasa Kondo asked about Golden Waveforms, stating that he thought most models already provided these. Michael responded that the [Test Data] and [Test Load] keywords allow including of silicon test or transistor-level simulation data for direct comparison to IBIS results. Unlike the V-T tables, these are not used in actual IBIS simulation. Yasumasa also asked whether the EDA vendor or the model distributor would be responsible for developing the code used by the API. Michael responded that likely the model distributor would be responsible for developing the code, much as the model distributor or author must extract table data today. Lance Wang made a few comments regarding circuit simulation and system simulation, agreeing that interest is increasing toward IBIS as a system- level analysis tool, in combination with C, Matlab* or other popular methods. He also added that an API could allow compilation for IP protection. SYSTEM-LEVEL TIMING CLOSURE USING IBIS MODELS Barry Katz, Signal Integrity Software (SiSoft) Barry provided an overview of the method used for analysis of timing at the system level. In particular, he focused on creating timing budgets using both knowledge of the system architecture (for the components and protocol) and derivations of timing equations before performing actual simulation. Design goals, interconnects and driver/receiver requirements all play a role. Signal integrity analysis permits the determination of the deviation between the ideal and realistic cases, including more effects. Further, an "executable" structured timing model can be used for both pre-route and post-route analysis. Barry concluded with an extended example using DDR2, where models, specifications and slew rate derating were combined to create detailed receiver eye diagrams. Yasumasa Kondo inquired about slew rate derating and whether this was possible in EDA tools such as SiSoft's. Barry noted that often slew-rate derating is built into DDR SI tools, but implementations vary. IBIS 4.2 and VHDL-AMS FOR SERDES AND DDR2 ANALYSIS Ian Dodd and Gary Pratt, Mentor Graphics (USA) Presentation was delivered by Minoru Ishikawa Minoru began by noting that traditional IBIS lacks features needed by modern buffer designs, such as pre-compensation and data recovery. He also noted that specialized measurements for these features do not exist in traditional IBIS either, but are now supported through the multi-lingual extensions. He compared SPICE and VHDL-AMS and Verilog-AMS as multi-lingual alternatives, stating that, while SPICE was popular, the *-AMS languages offer standardization and speed of simulation as advantages. Mixing the approaches may be a viable alternative. In two examples, Minoru showed that VHDL-AMS could be used to model a serial differential transmitter, simulating up to 10 million bits overnight. He also showed that IBIS 3.2 models could be combined with additional VHDL-AMS code to provide sophisticated measurements for interfaces such as DDR2. In both examples, he emphasized that both the *-AMS and SPICE macromodeling approaches in the industry today are viable, and that a combination of SPICE with IBIS 3.2-style models would be desirable to support under the IBIS specification. Tadashi Arai asked about the source for the data in the second case study. Minoru stated that this was based on customer measurement. Questions also arose regarding books or other support for learning *-AMS language techniques. Michael Mirmak noted that two textbooks currently exist for the languages, one for VHDL-AMS and one for Verilog-AMS. PDA FOR SI ANALYSIS IN LTI SYSTEMS - A VHDL-AMS CASE STUDY Arpad Muranyi and Michael Mirmak, Intel Corporation (USA) Michael Mirmak began by presenting the basic ideas of peak distortion analysis (PDA) for signal integrity. The essential concept is to perform successive overlays of eye responses from the pulse response of a driver-interconnect-receiver system, as measured at the receiver. For a linear, time-invariant (LTI) system, this can quickly provide a worst-case eye diagram for all data patterns, based on superposition. He showed how this analysis might be accomplished using VHDL-AMS, where analog time-domain simulations are used to produce a pulse response, and later "paint" the eye diagram result. Digital solving of the relevant equations is extremely fast, due to their analytic nature. The simple example shown did not include crosstalk, jitter or bit-error estimation. This work, plus efforts using Verilog-A/Verilog-AMS, is underway. Michael continued by noting the assumptions behind LTI analysis and how realistic systems might violate them. Buffers may not operate in the linear region, or may not be truly linear there. Both frequency-domain analyses and reflection analysis in the time-domain use the derivative or tangent of the I-V response of the buffer at the particular voltage of bias; they do not use the resistance of the I-V response at that voltage point. Therefore, an I-V table used as a terminator will create system responses that cannot be matched with a single resistance value for all bias voltages. This makes the system effectively non-LTI. Further, the buffer capacitance may change with voltage and state, making the driver, and therefore the system, non-LTI. This variance in impedance may also occur during transitions. Michael concluded by noting that buffer designers must be careful to observe LTI requirements, and asking whether a pulse response could be generated for a system without violating LTI requirements. ODT, PRE-EMPHASIS AND SPEED Bob Ross, Teraspeed Consulting Group Bob presented an overview of three issues affecting advanced IBIS models. He summarized his recommended approach to properly modeling on-die terminators as to "model the device structure." This means that mimicking the actual structure of an on-die terminator will usually prove most effective in properly representing its behaviors through IBIS I-V clamp tables, particularly when using his "Deviate, Extrapolate, Calculate" process. Bob also noted, through several examples, how a structural approach can be used to model pre-emphasis through the [Driver Schedule] keyword. He concluded by noting, through an extreme example, that no actual limit exists on the transition speed of the device modeled under traditional IBIS. CASE STUDY - SPICE MACROMODELING FOR PCI EXPRESS USING IBIS 4.2 Lance Wang, Cadence Design Systems Lance began by observing that the environment of PCI Express* in systems is particularly complex, with ISI effects being overcome through transmit equalization, or de-emphasis. In the particular example shown, de-emphasis was controlled through a 4-bit wide register, with voltage swing also having 4 bits of granularity plus high and low drive control. A SPICE macromodel using IBIS data was shown, where common and differential data was extracted for a differential buffer (in two stages) according to the IBIS 4.0 Cookbook. Additional IBIS structures were added to account for series pin-to-pin currents, while SPICE macromodeling code was used for the control inputs and the connections of the IBIS portions. Additional structures were added to improve correlation; these include an additional [Series Current] and Miller capacitances plus AC terminators. A comparison with a SPICE transistor-level model showed significant speed improvement where macromodeling was used. Lance concluded by recommending, in part, that IBIS should be opened to other commercial SPICE simulators under the multi-lingual extensions and that parameter passing should be enabled. STUDY OF INTERCONNECT MODEL Hiroaki Ikeda, Japan Aviation Electronics (Japan) Hiroaki presented the details of numerous experiments using measurement and simulation data. Eye diagram, vector network analyzer (for S-parameters) and TDR data was collected for comparison against four vendor's simulation tools. Test boards included differential pairs, vias, filters, a plane split and a connector, each tested separately. Simulation tool responses varied widely, with some showing excellent model-to-measurement correlation, with others showing considerable deviation. Further experiments are in progress. Lance Wang observed that poor correlation between simulation and measurement may be due to non-causal data in the interconnect models. SYSTEM-LEVEL SSO SIMULATION TECHNIQUES WITH VARIOUS IBIS PACKAGE MODELS Sam Chitwood, Jack W.C. Lin* and Raymond Chen, Sigrity (USA and *China) Presentation was delivered by Yutaka Honda of ATE Service Corporation. Yutaka showed the basic response of systems to simultaneously switching outputs (SSN). Total SSN is a combination of system, package and power delivery effects. Driver effects can be included through good models and appropriate switching patterns; IBIS models should include both [Pin Mapping] and split C_comp data. Of the several traditional IBIS methods for modeling package parasitics, per-pin and global lumped RLC were deemed inappropriate, due to the lack of coupling. The [Package Model] keyword can be used to include coupling, which can be made accurate using optimization. An extended set of DDR2 comparisons were shown, where 16 bits were toggled under various conditions. Yutaka concluded by suggesting that IBIS package information was good for "what-if" analysis, but that S-parameters were recommended for "highly accurate SSO sign-off." IBIS MODEL ENGINEERING FOR SI ANALYSIS Kazuhiko Kusunoki, Cybernet Systems (Japan) Kazuhiko began his presentation by noting that the number of users and usability of IBIS have been steadily growing over recent years. However, inefficient simulation procedures cost valuable time: rather than finding and correcting errors in IBIS after system simulations are complete, "front-loaded IBIS engineering" should rely on correcting errors in an IBIS early in the design process. These errors would include irregular data points, non-convergence issues in the V-T tables and clamp double-counting. He noted that this change in engineering emphasis would help prevent cases where relatively inexperienced engineers improperly use poor model data in simulation. He concluded by stating that such changes in approach would "help IBIS be more comfortable" for users and model makers. CONCLUDING ITEMS Michael Mirmak concluded the discussions by again thanking the co-sponsors, presenters and participants for the success of the Summit. He adjourned the meeting shortly before 3 PM. NEXT MEETING The next IBIS Open Forum teleconference will be held November 17, 2006 from 8:00 AM to 10:00 AM US Pacific Time. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-3788 michael.mirmak@intel.com Server Platform Technical Marketing Engineer, Intel Corporation FM5-79 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 01-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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