CONTENTS OF THE DESIGNCON EAST IBIS OPEN FORUM SUMMIT MEETING
April 5, 2004
Boxborough, MA

   .zip  Compressed
   .ppt, .pps  Power Point
   .doc  Word
   .ps   Postscript
   .pdf  Acrobat
   .txt  Text

ADMINISTRATIVE DOCUMENTS:

00readme.txt     This Document
a040504.txt      Agenda
m040504.txt      Minutes

PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):

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mirmak1.zip     IBIS Chair's Report and Roadmap (.ppt)
mirmak1.pdf     Michael Mirmak, Intel Corporation

haller.zip      IBIS Quality Specification Tour (.ppt)
haller.pdf      Bob Haller, Signal Integrity Software (SiSoft)

ross.zip        IBIS Hierarchactical Overrides and BIRD88 (.ppt)
ross.pdf        Bob Ross, Teraspeed Consulting Group
 
mirmak2.zip     Issues with C_comp and Differential Multi-stage
mirmak2.pdf     IBIS Models (.ppt)
                Michael Mirmak, Intel Corporation

wang.zip        Case Study: Using IBIS Buffer Models for
wang.pdf        Pre-Emphasis (.ppt)
                Lance Wang, Cadence Design Systems
 
muranyi.pdf     A VHDL-AMS Pre/De-emphasis Buffer Model
                Using IBIS 3.2 Data
                Arpad Muranyi, Intel Corporation

IBIS_PreDe.vhd  VHDL-AMS Code for Pre/De-emphasis Buffer Model