http://www.eda.org/pub/ibis/summits/dec05/agenda.pdf
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    A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

Time/Date:  8:00 - 17:30, Tuesday, December 6, 2005

Location:   Crowne Plaza Hotel Shenzhen
            9026 Shennan Rd, OCT
            Shenzhen, 518053
            CHINA
            Tel: 86-755-26936888
            Fax: 86-755-26936999
            E-mail: cpsz@cpsz.com
            http://www.ichotelsgroup.com/h/d/cp/1/en/hd/SZXNS

Room:       Crowne Plaza Ballroom #2, First Floor

Registration:  FREE, send to both addresses below:
            Name:
            E-mail address:
            Company:
            Telephone:

     Bob Ross, Teraspeed Consulting Group   bob@teraspeed.com
     Lance Wang, Cadence Design Systems     lwang@cadence.com


Sponsors:   Huawei Technologies (Primary)
            Cadence Design Systems, Mentor Graphics Corporation,
            Signal Integrity Software (SiSoft) and Sigrity

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       I B I S  S U M M I T  M E E T I N G  A G E N D A

8:15    REFRESHMENTS & SIGN IN
        - Vendor Tables Open

9:00    Introductions and Program Overview
        - Welcome, Jiang, XiangZhong, (Huawei Technologies, China)
        - Welcome to Summit, Mirmak, Michael (Intel Corporation, USA)
        - Welcoming Comments, Invited Chinese Leader/Speaker (China)

9:30    IBIS and Behavioral Modeling
        Mirmak, Michael (Intel Corporation, USA)

9:45    Fiberhome Telecommunications Technology Experiences with
        IBIS Models
        Zheng, Qi (Fiberhome Telecommunications Technology, China)

10:15   BREAK (Refreshments)

10:30   Simulation with IBIS in Tight Timing Budget Systems
        Sui, ShiJu, (ZTE Corporation, China)

11:00   Three Facets of IBIS: Interface, Behavior and Measurement
        Dodd, Ian* and Li, Henry** (Mentor Graphics Corporation,
        *USA and **China)

11:30   JEITA EDA - WG Activity and Study of Interconnect Model
        Watanabe, Takeshi* and Ito, Atsuji**, (*NEC Electronics
        Corporation, Japan and **Panasonic, Japan)

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)
        - Vendor Tables

        12:00 - 12:45 Press Conference for IBIS Officers and Sponsors

13:30   IBIS and Power Delivery Systems
        Jiang, XiangZhong, Li, JinJun, and Zhang, ShengLi (Huawei
        Technologies, China)

14:00   Power Delivery System, Signal Return Path and SSO Analysis
        Guidelines
        Chen, Raymond Y. and Chitwood, Sam (Sigrity, USA)

14:30   Splitting the C_comp for Power Integrity Simulations
        Yang, Zhiping (Apple Computer, USA)

15:00   Using IBIS for SI Analysis
        Wang, Lance* and Zhong, ZhangMin** (Cadence Design Systems,
        *USA and **China)

15:30   BREAK (Refreshments)

15:45   Macro Model and Multi-GHz System Simulation
        Zhu, ShunLin (ZTE Corporation, China)

16:15   IBIS Models for DDR2 Analysis
        Katz, Barry (Signal Integrity Software (SiSoft), USA)

16:40   Practical Measurement vs. Simulation Correlation with DDR2
        667 Interface
        Shoji, Kazuyoshi (Hitachi ULSI Systems Co., Japan)

17:05   Improving IBIS ECL Algorithms
        Ross, Bob (Teraspeed Consulting Group, USA)

17:20   Concluding Items

17:30   END OF IBIS SUMMIT MEETING
        - Final Vendor Tables and Teardown

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