DATE: 03/01/04 SUBJECT: February 20, 2004 EIA IBIS Open Forum European Summit Minutes VOTING MEMBERS AND 2004 PARTICIPANTS Ansoft Corporation (Eric Bracken) Apple Computer (To Be Determined) Applied Simulation Technology Norio Matsui Cadence Design Systems C. Kumar, Lance Wang, Patrick dos Santos* Cisco Systems Syed Huq Fairchild Semiconductor (Graham Connolly) Hitachi ULSI Systems Kazuyoshi Shoji* Huawei Technologies (Jiang Xiang Zhong) Intel Corporation David Keates, Peter T. Larsen Wilson Leung, Michael Mirmak, Arpad Muranyi, Steve Peterson LSI Logic Frank Gasparik Matsushita (Panasonic) Atsuji Ito Mentor Graphics John Angulo, Weston Beal, Ian Dodd, Guy de Burgh, Stephane Rousseau*, Eric Rongere* Micron Technology Paul Gregory, Randy Wolff Molex Incorporated (Gus Panella) Motorola (Rick Kingen) National Semiconductor (Lee Sledjeski) NEC Electric Corporation (Itsuki Yamada) North East Systems Associates Edward Sayre Philips Semiconductor (D.C. Sessions) Samtec (Corey Kimble) Siemens AG Eckhard Lenski*, Manfred Maurer* Siemens Medical (Acuson) David Lieby Signal Integrity Software Robert Haller, Barry Katz Sigrity Raymond Chen, Jiayuan Fang Sun Microsystems (Tim Coyle) Synopsys (Hailong Wang) Texas Instruments Hector Torres, Jean Claude Perrin* Teraspeed Consulting Group Tom Dagostino, Scott McMorrow, Bob Ross Time Domain Analysis Systems Steve Corey Zuken (& Incases) Ralf Bruening*, Laetitia Simonian*, Caroline Legendre* OTHER PARTICIPANTS IN 2004: Alcatel Jean-Pierre Bouthemy* Apache Design Yu Liu Bayside Design Daniel Lambalot, Kevin Roselle Conexant Garry Felker Cortina Systems Robert Badal EADS Olivier Maurice* Edality Rob te Nijenhuis* EFM Ekkehard Miersch Extreme Networks Lin Shen Fraunhofer IZM Ege Engin* GEIA (Chris Denham) Green Streak Programs Lynne Green Independent Kim Helliwell, Jon Powell INSA Etienne Sicard* Netlogic Microsystems Eric Hsu Politecnico di Torino Igor Stievano* Samsung Il Seong Silverback Systems Gil Gafni Sintecs BV Hans Klos* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode March 12, 2004 1-916-356-2663 1 837-4190 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. -------------------------------- MINUTES ----------------------------------- INTRODUCTIONS AND MEETING QUORUM The European IBIS Summit Meeting was held all day at CNIT La Defense in Paris, France along with the Design Automation and Test in Europe Conference (DATE04). About 17 people from 13 companies and institutes attended. The meeting presentations and other material are uploaded at: http://www.eda.org/pub/ibis/summits/feb04b/ Ralf Bruening opened the meeting and asked everyone to introduce themselves. The EDA tool vendors (6), model users and providers (9) and semiconductor vendors (2) groups were well represented. Ralf thanked the co-sponsors, Cadence Design Systems, Mentor Graphics and Zuken for sharing the meeting expenses. Ralf noted that several people who pre-registered informed him that they could not attend. PRESENTATIONS AND DISCUSSION TOPICS The rest of the meeting consisted of presentations and discussions. These notes capture some of the content and discussion. More details exist in uploaded documents in the link above. IBIS QUALITY Bob Haller, Signal Integrity Software (SiSoft), USA Presented by Eckhard Lenski, Siemens AG, Germany (Note, this presentation was also given at the IBIS Summit Meeting on February 2, 2004.) Eckhard Lenski showed the current status of the IBIS QUALITY document. He explained the different sections by using the index of the document and showed an example. The key idea behind the IBIS QUALITY document is its descriptions of quality levels. A level 0 model must pass the IBISCHK parser without errors. A level 1 model must also pass basic simulation testing with transmission lines and such. A level 2a model has been correlated in simulation with a transistor-level model. A level 2b model has been correlated in simulation with a model created from measurements. The level 3 model is correlates with both the transistor-level model and with measurements. In the discussion Shoji-San remarked, that there are too few IC vendors in the committee and that it also might be difficult for some vendors to achieve the FOM, which is a defined measure in the IBIS accuracy handbook. VERIFICATION OF IBIS MODELS Hans Klos, Sintecs BV, The Netherlands Hans Klos explained his company process to verify IBIS models. He showed that there are different ways to get models. Models from web pages are not always the latest version. Contact the IC vendors directly for the most recent models. The testing process includes using ibischk and using a free in-house tool, IBIS Development Studio, for visual inspection. This tool can be downloaded for free from the website of Sintecs. http://www.edality.com/ Another tool is used to manually change the V-I and V-T tables and to add missing parameters. Hans pointed out that the most important parameters are for over-shoot. Unfortunately, these are missing in most models. Vendors often do not respond to questions about these parameters, so he has to estimate them from the datasheet information. Models are also tested with different test loads. The final step in the verification process is to check them with measured data. SENSITIVITY ANALYSIS OF IBIS-PARAMETERS WITH HSPICE Manfred Maurer, Siemens AG, Germany Manfred Maurer noted that he has trouble getting appropriate IBIS models. The operating conditions he needs often differ from the ones he gets. For example, the model may have a Vcc tolerance, dVcc of +10%, but he may need a dVcc of +3%. So he is looking at using sensitivity analysis as a way of creating more accurate min-max-IBIS models to avoid analysis that is too pessimistic. One of his most important analysis parameters is the propagation delay of the signals on the PCB. Manfred is also concerned about the electrical, thermal and layout restrictions in his designs. He pointed out that HSPICE supports scaling V-I and V-T tables. He showed examples in the presentation of model variations and test fixture simulation differences. For a particular test case, he found that the fall time did not change much, but the rise time changed by about 300 ps. This needs to be investigated further. Sensitivity analysis allows for such investigation for design robustness. In the discussion he explained that much experience is needed to know which parameter to change and by how much. This may require knowledge of the internal silicon structure. IBIS MODELS, CURRENT STATUS (4.1) AND SOME NOTES ON IBIS VERSION 4.0 PARAMETERS Eckhard Lenski, Siemens AG, Germany Eckhard Lenski announced that IBIS 4.1 was approved at the end of January, 2004. The extension allows the use of [External Model]s encoded in SPICE, VHDL-AMS and Verilog-AMS. Eckhard explained that the [External Model] and the [External Circuit] keywords differ in the way that nodes are connected and parameters are passed. An [External Model] uses the connectivity and subparameters under the [Model] keyword while [External Circuit] requires encoding of connectivity and parameter information. Eckhard also stated that the ICM Version 1.0 Specification is released. Also s2ibis3 is advancing and ibischk4.0 is available. Eckhard discussed the new [Receiver Threshold] keyword. The subparameters Vth and Threshold_sensitivity come from the manufacturer. Vth, Vth_min, and Vth_max can also be derived from equations in the IBIS Version 4.1 Specification. Other subparameters were also discussed in detail. The IBIS Specification now contains 140 pages, a challenging prospect to new users of IBIS and to the industry as a whole. Eckhard expected improvements to continue regarding model availability, quality, accuracy, and tool independence. Several questions still exist, and he encourages tool vendors to adopt the advances faster. He felt that E-roadshows would be good for communicating the advances. IBIS & MODELING NEEDS FOR A FAST EMI & POWER INTEGRITY ANALYSIS OF PCB'S Ralf Bruening, Markus Buecker, Michael Schaeder, Zuken, Germany Presented by Ralf Bruening, Zuken Ralf Bruening gave an overview about the different sources for EMI: differential mode radiation, common mode radiation, power bus radiation, and IC noise. He then discussed the EMC Expert System approach from the EMC-Expert System Consortium headed by the University of Missouri, Rolla, USA. Its goal is to recognize critical areas and configurations, estimate potential radiation levels, and be usable within the design flow. The analysis should be fast (in minutes), but sufficiently accurate. The IBIS model contains V-T and I-V information, but it lacks I-T behavior. A 10% change in current may account for 1 dB difference in EMI, and a 100% change may account for 6 dB in estimated emission levels. Ralf discussed the parameters. He also discussed the power bus model, but noted that it is not considered in IBIS. But BIRD74.2 will bring useful information for EMI simulation. Ralf mentioned other approaches for EMI analysis including ICEM, SPICE, and IMIC. He concluded that more work is necessary, and EMI parameters must come from the semiconductor vendors. IC-EMIT: COMPARING SIMULATED/MEASURED IC EMISSION SPECTRUM Etienne Sicard, INSA, Amaury Souberyan, EADS, France Presented by Etienne Sicard Etienne Sicard introduced his presentation with a comparison of parasitic emissions of 8, 16, and 32 bit microcontrollers. Emissions increased when more internal transistors were switching. Etienne pointed out that INSA has created a freeware tool called IC Emit to help users simulate emission before fabrication. The tool is intended for a rough and quick estimation of the EMI of an IC where the fitting error of about 10% is acceptable. Etienne noted that the most significant contribution to EMI of an IC comes from core switching currents. Other current contributions are negligible. Etienne illustrated IC-Emit and showed two examples where the simulation and the measurement of EMI and ICs agreed. He explained how the tool uses IBIS models to create an ICEM-model. At this time there are just 20 models on the web, but more are coming. In the discussion he mentioned that some IC vendors have already started to supply real ICEM-models. LUNCH/DISCUSSION The group recessed for lunch paid by the sponsoring organizations. THE BENEFITS OF MULTI-LINGUAL EXTENSIONS TO IBIS Stephane Rousseau, Mentor Graphics, France Stephane Rousseau illustrated the benefits of using the newest version of IBIS (4.1). He gave an overview of the extensions and pointed out that IBIS supported multi-lingual modeling extensions are useful. He illustrated this point by examining a multi-gigabit output buffer with pre-emphasis. He showed several scenarios of mixing different modeling technologies. HSPICE simulation took about 21 minutes, but a simplified SPICE current steering circuit cut the time to 12 minutes. However, SPICE scaling options can conflict with other parts of the circuit. Stephane showed package model simplifications that further reduce the simulation time, but with some loss in overshoot detail. S-parameters were used for trace modeling. S-parameters may not provide DC information. These packaging and interconnect changes reduced the simulation time by 25%. The pre-emphasis buffer could be modeled using VHDL-AMS. This behavioral approach greatly reduced the simulation time by overcoming the need to simulate 1000's of nodes in the SPICE model. A chart showed the progressive simulation time reductions from 21 minutes down to 0.2 minutes. The results and corresponding eye diagrams showed good agreement. Stephane noted that IC vendors still need to be convinced to support VHDL-AMS models. He concluded that multi-lingual modeling in IBIS provides flexibility and performance improvements. During the discussion period, someone asked why not use the [Driver Schedule] keyword. Stephane responded that pre-emphasis values are not fixed, but could depend on the stimuli pattern and load conditions. With VHDL-AMS models, the proper selection can be automatic. With [Driver Schedule] the simulation setup involves manual processes. PARAMETRIC MODELS IN IBIS MULTILINGUAL FRAMEWORK F.G. Canavero, I.A. Maio, B. Ross*, I.S. Stievano, Politecnico di Torino, Italy, and Teraspeed Consulting Group*, USA Presented by Igor Stievano, Politecnico di Torino Igor Stievano gave an overview illustrating Macromodeling via Parametric Identification (pi) of LOGical Gates [M(pi)log] modeling. A model is formed mathematically in terms of the sum of any type of Basis Functions. This gives an alternative to IBIS Version 3.2 modeling since the fitting of the model to the basis functions can be done based on an expanded set of test conditions. He illustrated the approach with "tanh" basis functions. This approach is compatible with the multi-lingual IBIS Version 4.1 extension since the mathematical model can be programmed in a standard language such as VHDL-AMS. Igor showed two examples of how such a model is linked into IBIS. One example was a high speed CMOS driver, and the other was a differential buffer driving a differential test net. The behavioral simulation showed excellent correlation with the original SPICE simulations. Igor concluded that parametric models are easily implemented within the multi-lingual framework of IBIS. The advantages are a mathematical foundation, high accuracy with low complexity (like IBIS), good efficiency, and intellectual property (IP) protection. Advanced modeling techniques would require no further upgrade of IBIS. LUMPED SKIN EFFECT MODEL FOR PACKAGE LEADS A. Ege Engin, Fraunhofer Institute Reliability and Microintegration (IZM) and University of Paderborn, Germany Ege Engin introduced the need for skin effect modeling of packages. He noted that it degrades rise and fall times. Ege provided an overview of previous work to model skin effect. The overview included methods based on PEECs, coaxial lines, ladder networks, Foster-type models, and ideal skin effect formulations. He compared their advantages and disadvantages. The ideal skin effect formulation can be described using a continued fraction expansion (CFE) of an LG structure of a transmission line. (G=1/Rdc.) Ege showed that accuracy improves with more CFE tags, and the Ldc correction term for internal inductance produces overlaying complex impedance versus frequency comparisons. With eight stages, the accuracy is within 2% over three decades of frequency beyond the transition frequency region where Rac=Rdc. Each doubling of the number of stages tends to extend the accuracy through another decade. Ege discussed how improvements could be implemented within IBIS. He discussed the existing package keywords [Inductance Matrix] and [Resistance Matrix], the ICM S-parameter format and the [External Circuit] approach. Ege proposed using Rac, Rdc, and Ldc matrices and extraction frequency. During the discussion, the group suggested that Ege make his work visible to the US IBIS community and propose a BIRD for the suggested improvement to model skin effect. CONCLUDING REMARKS Ralf Bruening thanked the presenters and the sponsors for their help and support in making the meeting successful. The next DATE conference and associated European IBIS Summit Meeting will be in Munich, Germany in 2005. Ralf then adjourned the meeting. NEXT MEETING The next Open Forum teleconference was held in the US later on the same day in a different time zone (February 20, 2004 from 8:00 AM to 10:00 AM US Pacific Standard Time). The next Open Forum teleconference has been scheduled for March 12, 2004 from 8:00 AM to 10:00 AM US Pacific Standard Time. ======================================================================== NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046 michael.mirmak@intel.com Senior Analog Engineer, Intel Corporation M/S FM6-45 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 788-4289 lgreen22@mindspring.com Green Streak Programs 20130 181st PL NE Woodinville, WA 98077 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 1-711 Boise, ID 83707-0006 LIBRARIAN: Roy Leventhal (847) 590-9398 roy.leventhal@ieee.org Consultant, Leventhal Design and Communications 1924 North Burke Drive Arlington Heights, Illinois 60004 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008 John_angulo@mentor.com Development Engineer, Mentor Graphics 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. 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