CONTENT OF THE EIA IBIS OPEN FORUM SUMMIT MEETING
February 1, 2007
Santa Clara, California

   .zip  Compressed
   .ppt  Power Point
   .doc  Word
   .ps   Postscript
   .pdf  Acrobat
   .txt  Text

ADMINISTRATIVE DOCUMENTS:

00readme.txt    This Document
a020107.txt     Agenda
m020107.pdf     Minutes

PICTURES:


pictures/       Meeting Pictures
                Michael Mirmak, Intel Corporation


PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):

mirmak.zip      IBIS Chair's Report and Issues Summary (.ppt)
mirmak.pdf      Michael Mirmak, Intel Corporation

labonte.zip     Study of IBIS Waveform Time Offsets (.ppt)
labonte.pdf     Mike LaBonte, Cisco Systems, Inc.

wang.pdf        Initial Time Delay Issue in IBIS VT Curves
                Lance Wang, Cadence Design Sysems

helliwell.zip   IBIS Quality Committee Report (.ppt)
helliwell.pdf   Kim Helliwell, LSI Logic

ross.zip        X (.ppt)
ross.pdf        Bob Ross, Teraspeed Consulting Group

boluna.pdf      DFE Modeling Using IBISv4.2/VHDL-AMS
                Luis Boluna, Ehsan Kabir, Susmita Mutsuddy and
                AbdulRahman Rafiq, Cisco Systems
                (Presented by Luis Boluna, Cisco Systems)
 
muranyi.pdf     Statistical Eye Analysis Implemented in VHDL-AMS
                Arpad Muranyi, Intel Corporation
                (Revised February 12, 2007)

  Stateye_Project.zip
                Package of code modules associated with presentation
                See readme.txt in the package
                Arpad Muranyi, Intel Corporation
                (Updated June 26, 2007)

  old/          Subdirectory containing the original presentation
                and original Stateye_Project_zip given at meeting
                
sudarshan.zip   IBIS Modeling of USB Buffers (.ppt)
sudarshan.pdf   HN Sudarshan, NXP Semiconductor

westerhoff.zip  IBIS Advanced Technology Modeling Group (IBIS-ATM)
westerhoff.pdf  Status Report (.ppt)
                Todd Westerhoff, Signal Integrity Software (SiSoft)