CONTENT OF THE EIA IBIS OPEN FORUM SUMMIT MEETING February 7, 2008 Santa Clara, California .zip Compressed .ppt Power Point .doc Word .ps Postscript .pdf Acrobat .txt Text ADMINISTRATIVE DOCUMENTS: 00readme.txt This Document a020708.txt Agenda m020708.pdf Minutes m031408.pdf Correction to Minutes PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION): mirmak.zip IBIS Chair's Report and Roadmap (.ppt) mirmak.pdf Michael Mirmak, Intel Corporation wang.pdf Waveform Comparison and S2IBIS3 Roadmap Lance Wang, Cadence Design Sysems wolff.zip Modeling DDR3 with IBIS (.ppt) wolff.pdf Randy Wolff, Micron Technology chitwood.pdf Proper IBIS Package Modeling Techniques and Usage in Ideal PDS and SSO Simulations Sam Chitwood, Sigrity ross1.zip Touchstone Syntax for Versions 1.0 and 2.0 (.ppt) ross1.pdf Bob Ross, Teraspeed Consulting Group rao.zip New Interconnect Models Remove Simulation rao.pdf Uncertainty (.ppt) Fangyi Rao*, Chad Morgan**, Vuk Borich* and Sanjeev Gupta*, *Agilent Technologies and **Tyco Electronics (Presented by Chad Morgan** and Fangyi Roa*) ross2.zip Multi-Mode Modeling (.ppt) ross2.pdf Bob Ross, Teraspeed Consulting Group shelpnev.zip Buidling Advanced Transmission Line and Via-hole shelpnev.ppf Models for Serial Channels with 10 GBps and Higher Data Rates (.ppt) (With notes) Yuriy Shelpnev, Simberian boluna.pdf Advances in 7.5Gb/s SerDes Modeling using IBISv4.2(VHDL-AMS and Verilog-AMS) Luis Boluna*, Kelvin Qiu*, Ehsan Kabir*, Susmita Mutsuddy*, Daniel Ho*, and Dr. Sang Baeg**, *Cisco Systems and **University of Hanyang (South Korea) (Presented by Luis Boluna, Cisco Systems) muranyi.pdf IBIS-AMI with Different Languages Arpad Muranyi, Mentor Graphics Corporation westerhoff.pdf Serdes Modeling: Demonstrating IBIS-AMI Model Interoperability Todd Westerhoff, Signal Integrity Software (SiSoft) hawes.pdf Experiences in Developing and Correlating Eight Interoperable Algorithmic Models Adge Hawes* and Ken Willis**, *IBM and **Cadence Design Systems (Presented Adge Hawes* and C. Kumar**)