CONTENT OF THE IBIS OPEN FORUM SUMMIT MEETING
February 1, 2019
Santa Clara, California

   .zip         compressed
   .ppt, .pptx  PowerPoint
   .doc, .docx  Word
   .pdf         Adobe Acrobat
   .txt         Text

ADMINISTRATIVE DOCUMENTS:

00readme.txt    This Document

a020119.txt     Agenda
a020119.htm
agenda.docx

m020119.docx    Minutes
m020119.txt

backdrop.pptx   Meeting Backdrop

PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):

labonte.pdf   IBIS Update
labonte_a.pdf DesignCon 2019 IBIS Mentions
              Mike LaBonte (SiSoft, USA)

kawata.pdf    JEITA EDA Model Specialty Committee Report
              Miyo Kawata (ANSYS, Japan)

muranyi.pdf   IBIS-ATM Task Group Report
              Arpad Muranyi (Mentor, a Siemens Business, USA)

mirmak.pdf    Introducing IBIS Version 7.0
              Michael Mirmak (Intel Corporation, USA)

ross.pdf      IBIS Version 7.0 Hierarchy Additions
              Bob Ross (Teraspeed Labs, USA)

tanaka.pdf    IBIS V7 and IEEE 2401 Harmonization
              Genichi Tanaka, (Renesas, Japan)
              for (JEITA_Semiconductor and System Design Technical Committee

wu.pdf        COM & IBIS-AMI: How They Relate & Where They Diverge
              Hsinho Wu, Masashi Shimanouchi, Mike Li (Intel Corporation, USA)
              [Presented by Hsinho Wu (Intel Corporation, USA)

dmitriev-zdorov.pdf
              Baseline Wander, Its Time-domain and Statistical Analysis
              Vladimir Dmitriv-Zdorov (Mentor, a Siemens Business, USA)

willis1.pdf   Channel Simulation Using IBIS models with Asymmetric Rising
              and Falling Edges
              Ken Willis, Kumar Keshavan, Ambrish Varma (Cadence Design Systems, USA)
              [Presented by Ken Willis (Cadence Design Systems, USA)]

katz.pdf      Methods to Reduce Effects of DDR5 Rise/Fall Asymmetry in IBIS-AMI
              Simulations
              Walter Katz (SiSoft, USA)

mido.pdf      Study on Potential Feature Additions for Bit-by-bit Simulation
              Technique to Address DDR5 Requirements
              Ted Mido (Synopsys, Japan)

huang.pdf     Study of DDR Asymmetric Rt/Ft in Existing IBIS-AMI Flow
              Wei-hsing Huang* and Wei-kai Shih** (SPISim, *USA, **Japan)

butterfield.pdf
              Modeling Forwarded Clock Interfaces with IBIS-AMI
              Justin Butterfield (and Randy Wolff?? (Micron Technology, USA)

slater.pdf    Rx Clock Forwarding Investigation
              Stephen Slater (Keysight Technologies, USA)

willis2.pdf   Impact of True Strobe Timing on DDR Channel Simulation with IBIS-AMI Models
              Ken Willis, Kumar Keshavan, Ambrish Varma (Cadence Design Systems, USA)
              [Presented by Ambrish Varma (Cadence Design Systems, USA)

murata.pdf    On Die De-cap Modeling Proposal
              Kazuki Murata*, Megumi Ono** (Ricoh*, Socionext**, Japan)
              (JEITA_Semiconductor and System Design Technical Committee)
              [Presented by Megumi Ono (Socionext, Japan)]

yang.pdf      IBIS Based Modeling for System-Level Power Delivery
              Zhiping Yang*, Songping Wu*, Kinger Cai**, Joshua Luo***, Yingxin Sun***
              (Google*, Intel Corporation**, Cadence Design Systems***; USA)
              [Presented by Zhiping Yang (Google, USA)]