------------------------------------------------------------------ AGENDA, IBIS SUMMIT MEETING January 31, 2005 Santa Clara Convention Center Santa Clara, California Room: Magnolia Room, Westin Hotel (check signs at site) ------------------------------------------------------------------ 8:00 AM Refreshments & Sign In 8:30 AM Introductions - Welcome to Summit - Introductions - IBIS Booth 940 - Opens for Issues, Discussion Topics 8:45 AM IBIS Chair's Report and Roadmap Michael Mirmak, Intel Corporation 9:00 AM IBIS Quality Committee Report Kim Helliwell, Silicon Bandwidth, Inc. 9:30 AM An Initial Case Study for BIRD95 - Enhancing IBIS for SSO Power Integrity Simulation Sam Chitwood, Raymond Chen, Jiayuan Fang Sigrity Inc. 10:00 AM BREAK 10:15 AM BIRD95 and Power Integrity Validation using HSPICE Syed Huq, Vinu Arumugham, Dr. Zhiping Yang Cisco Systems, Inc. 10:45 AM BIRD95 Technical Discussion - All Syed Huq, Vinu Arumugham, and Dr.Zhiping Yang Cisco Systems, Inc. 12:00 PM LUNCH - (Hosted by DesignCon) Pre-registration required 1:00 PM IBIS Power/Ground Modeling of LSI Core Logic with High Pin Count Package for EMI and PI Norio Matsui, Applied Simulation Technology Hiroshi Wabuka, NEC 1:30 PM Modeling Pre/De-emphasis Buffers with [Driver Schedule] Arpad Muranyi, Intel Corporation 2:00 PM Modeling Complex IOs with IBIS 4.1 Donald Telian, Cadence Design Systems 2:30 PM Stacked Package Modeling with IBIS Version 4.1 Tom Dagostino and Bob Ross, Teraspeed Consulting Group 3:00 PM BREAK 3:15 PM Practical Issues in Enabling a Corporate IBIS Library Todd Westerhoff, Cisco Systems, Inc. 3:45 PM A Preview of the IBIS 4.0 Cookbook Michael Mirmak, Intel Corporation 4:15 PM Searching the WWW for Spice and IBIS Kellee Crisafulli, CelsioniX, Inc. 4:45 PM Opens/Discussion 4:55 PM Concluding Items - Next Open Forum Meeting: February 18, 2005 - DATE 2005: March 11, 2005, Munich, Germany 5:00 PM End of IBIS Summit Meeting ------------------------------------------------------------------ REGISTRATION INFORMATION People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Send to: Syed Huq(shuq@cisco.com) Lunch registration is separate. To register for lunch, you must be registered for DesignCon (information at ). ------------------------------------------------------------------ Sponsors: DesignCon, Cisco Systems and Cadence Design Systems DesignCon: January 31-February 3, 2005 Santa Clara Convention Center Santa Clara, California See for more information. LIST OF NEARBY HOTELS See for travel directions, hotels and other information.