DATE: 07/31/06 SUBJECT: July 25, 2006 EIA IBIS Summit (DAC) Minutes VOTING MEMBERS AND 2006 PARTICIPANTS Actel (Prabhu Mohan), Ann Lau* Agere (Nirav Patel) Agilent Sanjeev Gupta, Nilesh Kamdar AMD [Wasim Ullah], Tadashi Arai Ansoft Corporation Michael Brenneman Apache Design Solutions Ji Zheng* Applied Simulation Technology Fred Balistreri Cadence Design Systems Lance Wang* Cisco Systems Syed Huq*, Mike Labonte* AbdulRahman Rafiq*, Pedo Miran Salman Jiva, Gurpreet Hundal Todd Westerhoff Fluent (Chetan Desai) Freescale (Jon Burnett) Green Streak Programs Lynne Green* Hitachi ULSI Systems Kazuyoshi Shoji* Huawei Technologies (Xiangzhong Jiang) Integrated Circuit Systems (ICS) (Dan Clementi) Intel Corporation Michael Mirmak*, Arpad Muranyi*, Stephen Peters, Vishram Pandit LSI Logic Frank Gasparik, Kim Helliwell* Praveen Soora* Marvell (Itzik Peleg) Mentor Graphics John Angulo*, Ian Dodd*, Gary Pratt* John Shields*, Simon Vines [Guy de Burgh] Micron Technology Randy Wolff NEC Electronics Corporation Takeshi Watanabe* Panasonic Atsuji Ito Samtec (Corey Kimble) Siemens AG Eckhard Lenski, Manfred Maurer Katja Koller, Klaus Huebner, Heinz-Hartmut Ibowski, Flavio Maggioni, Roberto Preatoni Siemens Medical David Lieby Signal Integrity Software Barry Katz, Douglas Burns, Mike Mayer Walter Katz, Kevin Fisher Sigrity Sam Chitwood, Raymond Chen* Silego (Joe Froniewski) Silicon Image (Ook Kim) STMicroelectronics (Antonio Girardi) Synopsys Andy Tai*, Ted Mido Teraspeed Consulting Group Bob Ross* Texas Instruments Otis Gorley, Richard Ward* Toshiba Yasumasa Kondo*, Yoshishiro Hamaji* Motochika Okano* Xilinx (Ray Anderson) Zuken Michael Schaeder, Ralf Bruening OTHER PARTICIPANTS IN 2006: Altera Khalid Ansari Amkor Technology Nozad Karim Ashenden Designs Peter Ashenden* Apple Computer [Zhiping Yang] Betty TV Stephanie Goedecke Bosch Ingo Doerr, Jurgen Hasch Cybernet Systems (KAW) Kazuhiko Kusunoki, Azusa Harada* Toshiyo Saito*, Keiji Soyama* EFM Ekkehard Miersch Dell Aubrey Sparkman Force10 Networks Robert Badal Free Electron Software Al Davis* GEIA (Chris Denham) IBM Lance Thompson* Infineon Radovan Vuletic, Minka Gospodinova Christian Sporrer, Amir Motamedi JEITA Atshushi Ishikawa* Leventhal Design Roy Leventhal Lynguent Andrew Levy NCSU Paul Franzon* Philips Herve Menager* Politecnico di Torino Igor Stievano Rambus Nirmal Jain Samsung Heeseok Lee, Il Seong* SimLab Heiko Grubrich Vectronix AG Luca Giacotto In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode August 4, 2006 1-916-356-2663 1 868-6175 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- WELCOME AND INTRODUCTIONS The IBIS Open Forum Summit was held in San Francisco, California at the Argent Hotel during the 2006 Design Automation Conference (DAC). About 34 people representing 23 organizations attended. The notes below capture some of the content and discussions. The meeting presentations and other documents are available at: http://www.eda-stds.org/summits/jul06/ Michael Mirmak opened the Summit meeting by thanking the co-sponsors, Cisco Systems, Green Streak Programs and Mentor Graphics, for their financial and logistical support. Michael asked each of the participants to introduce himself and state his length of involvement with IBIS. IBIS CHAIR'S REPORT AND ROADMAP Michael Mirmak, Intel Corporation Michael began the formal agenda of presentations by summarizing the most recent achievements by the IBIS organization, including the passage of IBIS 4.2 and release of an accompanying parser. GEIA and ANSI balloting of the specification is underway. He noted that the financial state of the organization is excellent and that planning is proceeding on October summits in China and Japan. Finally, he noted that the work on IBIS 5.0 will take most of the time between now and the next DAC IBIS Summit, as the BIRDs still pending are highly complex and require considerable attention. IBIS QUALITY DESIGNATIONS Mike LaBonte, Cisco Systems Mike reported on the current designations used by the IBIS Quality team to classify models: these range from IQ 0 (passing the parser) to IQ 3, where all correlation checks have been passed. A new set of quality levels has been proposed, where IQ 0 would correspond to an "unknown" or minimal/unchecked level of quality. Increasing levels would signify increasing numbers of passed checks, starting with the parser. Additional letter designations would be used to state that exemptions had been granted for warnings and what kinds of corrleations had been used to validate the model. For example, level 2SX would mean level 2, simulation correlated, but with some warning exceptions documented. Mike noted that the new designations had not been formally voted by any body. He also observed that the Quality team continues to follow the IBIS Accuracy Specification recommendations as listed. MACROMODELING COMMITTEE ACTIVITIES Arpad Muranyi, Intel Corporation Arpad reported on the latest achievements of the IBIS Macromodeling Committee. Work completed includes VHDL-AMS and Verilog-A libraries of standard buffer modeling building blocks, plus templates for common model types. One recent issue encountered is that more complex building blocks are needed for advanced SERDES buffers, to model clock recovery and similar features. While "phase 1" of the library building effort addresses the concerns raised by Donald Telian in his macromodeling presentation in 2005, the "phase 2" work will be to develop more complex templates to cover these advanced SERDES features. Additionally, the team has addressed encryption standards, but is leaving detailed development to the IEEE and Accelera groups already refining a standard. Finally, the team is reviewing proposals to use an API-based approach to SERDES system modeling (covered later) and is actively evaluating this against an AMS-based solution. Such an API would permit any language to be used, but enforce a compiled format connection to tools (for example, a simple C-based wrapper around the model core). Questions arose from the attendees about specifics, including SystemC or SystemVerilog. Arpad suggested that the task group investigation is just beginning and further work is required. Ian Dodd noted that AMS is not necessarily ruled out as a continuing solution, as it does not natively increase simulation time. SPICE-based solvers must resolve conductance matrices, which grow larger and slow down the sim as they grow. AMS-based models add few nodes to the solution requirements, rather than dramatically increasing matrix size. A STANDARDS-BASED APPROACH TO IP PROTECTION FOR HDLS John Shields, Mentor Graphics John provided a primer on protecting IP through encryption. In essence, how does one deliver IP to customers one doesn't wholly trust? Most EDA-oriented encryption schemes rely on decryption at the tool level, where some sort of secret key (either symmetric private or asymmetric public/private pairs) are used. Symmetric solutions are much faster though more easily compromised than asymmetric ones. Further, data may be enclosed in a "digital envelope" to permit "signing" of the data and adding some assurance of authenticity. John noted that key management becomes an issue, as keys may be created per model, per customer or in other ways. John concluded by summarizing a proposed standard approach to EDA encryption, that creates "tick"-based keywords for encryption method, key owner, information regarding the envelope used and other data. Not being limited to a particular language, both AMS variants could use the standard. Currently, the standard is under review in several specification bodies. Arpad inquired regarding obfuscation, to which John responded that reverse-engineering of obscured code is possible with a "code understanding" tool. Lynne Green suggested that IBIS model review after encryption could be made impossible under such a standard. Michael inquired about support for encryption standards between tools outside of the DES minimum requirement. John agreed this was a potential hurdle, but necessary to permit maximum adoption of the standard. During the discussion, guests Lance Thompson, Accellera's VHDL technical committee chair, and Peter Ashenden, author of VHDL texts and committee document editor, introduced themselves. SERDES INTRODUCTION AND MACRO/AMS MODELLING Richard Ward, Texas Instruments Richard began by observing the proliferation of serial- differential interface standards and the increasing speed of these interfaces. At 6.25 Gbps, the "eye" seen in the middle of the channel is vanishingly small, requiring filtering, equalization and other techniques to reproduce it. Large backplanes using FR4 material and long cables are forcing more creative ways of driving and reconstructing signals by devices. Richard noted that AMS is of some interest in buffer modeling, and that S-paramter data is increasingly used for channel characterization. However, variable timesteps used in convolutions mean errors tend to increase when S-parameter data is used. Further, while bit-error rate (BER) and statistical analyses from the frequency domain are useful, non-linearities in the buffers mean that significant time-domain simulations are still run and his team is therefore moving away from purely statistical analyses. The buffers are treated as "event engines" vs. the "error engine" of the channel. The analysis he favors is a two phase approach: one phase to perform several million unit intervals of time-domain simulations, then use waveform processing to extrapolate behaviors (likely the frequency domain). A direct BER method using trillions of bits is not computationally feasible. Calling S-parameters under AMS or SPICE is an option for channel descriptions. Ian Dodd noted that some S-parameter convolution implementations do not necessarily use a fixed timestep. Some debate ensued whether the use of a variable timestep approach is to increase accuracy or simulation speed. ALGORITHM MODELING APPROACH FOR SERDES DEVICES Lance Wang, Cadence Design and Joe Abler, IBM Lance presented a proposal for treating advanced SERDES interfaces algorithmically, rather than through component-based modeling techniques. Structural models, including SPICE, have insufficient speed or capacity to capture all the necessary circuit elements and that direct equation-based modeling was effectively impossible structurally. Lance suggested that AMS-based solutions lacked capacity, IP protection and were better suited to circuit modeling rather than toward entire systems. For future growth, advanced filtering, equalization and other techniques must be supported beyond reference load approach used today, though linearity remains, according to Lance, a valid assumption. His proposal uses a C-wrapper around DLL-based data for the devices and waveform processing algorithms. Experiments showed eye opening predictions, capturing crosstalk and other effects while minimizing simulation time. An API-based approach could be standardized to allow cross-tool deployment. ELECTION OF OFFICERS Michael summarized the offices used by the IBIS Open Forum and called for nominations for each, in addition to showing the slate of candidates who had already announced their intention to run. These were: Chair: Michael Mirmak, Intel Corporation Vice-Chair: Syed Huq, Cisco Systems Secretary: Randy Wolff, Micron Technology Webmaster: Syed Huq, Cisco Systems Postmaster: Bob Ross, Teraspeed Consulting Group Model Librarian: Lance Wang, Cadence Design Systems Michael noted that the chair also fulfills the duties of treasurer for the organization. Elections for all offices except that of Model Librarian were uncontested and approved by voice-vote acclimation. Lynne Green of Green Streak Programs nominated herself as an additional candidate for Model Librarian. Lance Wang was re-elected on a vote of 8 to 3, with 1 abstention. SPICE2IBIS - STATUS AND PLANNED IMPROVEMENTS Paul Franzon, North Carolina State University Paul reviewed a new approach, developed by Ambrish Varma, for including power delivery effects in simulations with IBIS data beyond that possible under BIRD95. This method models SSO as a "compromise" between a macromodel and a "black box" behavioral model, using a second-order polynomial to correct the current from the source supply. This compensates for the IBIS tendency to overpredict edge rate and overshoot in SSO simulations. A 25% improvement in matching SPICE results over previous methods was noted. Paul also reported on the status of SPICE2IBIS. Over 400 hits on SPICE2IBIS in its lifetime have been noted. However, with Ambrish leaving NCSU, support for the program may cease. As DARPA support is unlikely in future, other models for financing SPICE2IBIS development must be investigated, including a "charge" model, a consortium-based development group or even establishing relationships with EDA tool vendors (this last was rated most likely to work). Paul will continue discussions with the IBIS Open Forum over other fund sources. Al Davis suggested posting code on SourceForge, as has been done with driver software and AMS models, to ensure continued public development. BUFFERS FOR ADVANCED SPICE TO IBIS TESTING Bob Ross, Teraspeed Consulting Group Bob presented an overview of simple SPICE circuits that mimic IBIS model types, to enable testing of key IBIS concepts. The circuits rely on Level 2 Berkeley SPICE CMOS and ECL models, with controlled sources and diodes to represent all but the most complex buffer behaviors. The models permit validation of several IBIS algorithms related to clamp extension, subtraction and "clipping," as well as examination of IBIS creation tools such as SPICE2IBIS. IBIS IN THE FREQUENCY DOMAIN Michael Mirmak, Intel Corporation Michael presented an overview of key ideas related to frequency domain usage of IBIS models. He reviewed proper duration of V-t tables vs. the maximum swtiching frequency of an interface; the limitations of single-valued C_comp; the error of assuming a passive-only model of a receiver or driver; and the distinction between maximum switching frequency and maximum edge rate. Several "pitfalls" related to these areas may be encountered during IBIS data extraction from a buffer design. Maximum edge rate, however, can also apply to the entire interface, particularly if the buffer design is much faster than the original assumptions of the interface specification (e.g., SMBus*). In general, he advised that "native" IBIS can be used without modification for lower speed and lower edge rate interfaces. Care must be taken with today's higher speed interfaces and several aspects of frequency domain analysis imply that key native IBIS assumptions are no longer valid. AMS or even table-based models may be needed for complex C_comp and/or buffer impedance representations in the future. GATE MODULATION EFFECT AND BIRD97/98 Arpad Muranyi, Intel Corporation Arpad summarized recent work in analyzing SPICE models of simple 5 volt buffers to account for power supply currents as done in BIRD95. To do this accurately requires some calculation of gate modulation and its effects on the output. To illustrate the effects, Arpad showed both high and low state output behaviors of the buffer as the supply voltage was stepped at different rates from 5 to 4 volts. In the SPICE circuit, a clear RC effect can be seen, which even a Verilog-A model based upon a two-equation, two-unknown algorithm could not match. Splitting the C_comp between power and ground rails helped but did not entirely match the SPICE behavior. Arpad noted that the actual behavior appears to be Miller capacitance linking the Ron of the predriver with the circuit formed by the buffer I-V data and C_comp. Adding higher-order RC circuits could help slightly, but not match the SPICE model. Arpad concludes that the use of static scaling coefficients (k-factors) for transitioning buffers is "bogus" and that, to account for the gate modulation effect, a new set of IBIS assumed equations and algorithms must be developed. DDR2 ELECTRICAL AND TIMING MEASUREMENTS IN VHDL-AMS Gary Pratt, Mentor Graphics Using the film "2001: A Space Odyssey" as a theme, Gary summarized an approach to using VHDL-AMS as a measurement method as opposed to modeling buffer behavior. In this case, IBIS models were used in a beta simulation tool constructed to simulate a DDR2 interface. With VHDL-AMS modules to measure overshoot, undershoot and various edge rate parameters. The approach could be used for a multi-component system, but a means would have to be implemented to communicate the exact reference designator of the part being reported to the tool. A key limitation of the algorithm shown is that, to measure DDR2 specification parameters in real time, a proprietary analog solution point (ASP) variable is used to synchronize the analog and digital solution engines. Some discussion erupted over whether this would be necessary for all tools and whether the VHDL-AMS (IEEE 1076.1) specification could be enlarged to include it. NEW NEEDS FOR MEASUREMENTS AND PARAMETER PASSING IN IBIS Ian Dodd, Mentor Graphics Ian provided a complementary view of measurement in simulation to that presented by Gary Pratt. From the perspective of future specification development, IBIS can either enable AMS-based measurements or define a minimum set of descriptors for measurement data to be returned to tools, including keyword, a description, the usage, data type and valid range expected. Ian provided both IBIS and AMS-based examples. Usage may be the most difficult descriptor to provide, as it can range from pass/fail criterion to general information report. The approach to avoid is that used for [Model Selector], where buffer descriptions are repeated for relatively small changes in state. Any user-defined measurements would also have to include some sort of default value assumptions. IBIS SUMMARY AND EVOLUTION Bob Ross, Teraspeed Consulting Group Bob provided a brief overview of the evolution of IBIS keywords over versions of the specification since 1.1. He also summarized the current state of the specification's keywords, noting the tight integration between them: each keyword and subparameter introduced is unavoidably linked to many others. He cautioned those contributing new keywords that current specifications must be examined extremely carefully to avoid creating conflicts with existing keywords. Some discussion ensued as to whether all the current keywords would be maintained in IBIS 5.0. OPENS/DISCUSSION Michael opened the floor for discussion of opens as well as issues that were tabled earlier in the day. Michael noted that Gary's presentation implied that eventually all aspects of IBIS could be replaced with AMS-based code. Several agreed this was possible, with Ian Dodd noting that this was one option among many, including enhancing existing IBIS with more robust measurement parameters. Al Davis noted that IBIS-X would have taken some of this into account. Bob Ross objected to the idea that IBIS could "fade away," suggesting that IBIS as a signal integrity modeling application might remain useful even if industry moves beyond the AMS languages. Michael adjourned the meeting shortly after 5 PM. NEXT MEETING The next IBIS Open Forum teleconference will be held August 4, 2006 from 8:00 AM to 10:00 AM US Pacific Time. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-3788 michael.mirmak@intel.com Server Platform Technical Marketing Engineer, Intel Corporation FM5-79 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 01-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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