DATE: 7/1/02 SUBJECT: June 23, 2003 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 2003 PARTICIPANTS LIST: Ansoft Corporation (Eric Bracken) Apple Computer Kim Helliwell Applied Simulation Technology Fred Balistreri Cadence Design Lynne Green*, Lance Wang* Cisco Systems Syed Huq, Michael LaBonte*, Val Mandruson, Hung Pham, Todd Westerhoff* Fairchild Semiconductor (Graham Connolly) Hitachi ULSI Systems Kazuyoshi Shoji* Intel Corporation Stephen Peters*, Michael Mirmak*, Arpad Muranyi*, Eric Magnusson LSI Logic Frank Gasparik Matsushita (Panasonic) Atsuji Ito Mentor Graphics [Bob Ross], Ian Dodd*, Guy de Burgh, John Angulo, Weston Beal, Mike Donnelly, Micron Technology Randy Wolff Molex Incorporated Gus Panella Motorola (Rick Kingen) National Semiconductor [Milt Schwartz], [Tim Coyle] NEC Electric Corporation (Itsuki Yamada) Philips Semiconductor (D.C. Sessions), Stephanie Goedecke Siemens (& Automotive) AG Eckhard Lenski, Michael Kindij, Burkhard Muller, Katja Koller, Andre Goerisch, Manfred Maurer, Bernard Unger, Amir Motamedi, Hartmut Ibowski, Gerald Bannert Signal Integrity Software Bob Haller*, Barry Katz*, Doug Burns Sigrity [Raj Raghuram] Synopsys Warren Wong, Edmund Cheng Texas Instruments Thomas Fisher Teraspeed Scott McMorrow*, Tom Dagostino*, Kevin Simpson, Bob Ross* Time Domain Analysis Systems Dima Smolyansky, Steve Corey Zuken (& Incases) Michael Schaeder, Ralf Bruening OTHER PARTICIPANTS IN 2003: Agilent Technologies Herbert Lage Brocade Frank Yuan, Yongrue Yu Conexant Gary Felker EADS CCR Alix de la Villeguerin EFM Ekkehard Miersch EMC Corporation Brian Arsenault*, John Fernandez*, Simba Julian* Fraunhofer IZM Ege Engin Fujitsu Tadashi Arai GEIA (Chris Denham) Huawei Technologies (Jiang Xiang Zhong) Independent Kelly Green, Luca Giacotto Infineon Tech AG Christian Sporrer Marvell Semiconductor Itzik Peleg NetLogic Microsystems Eric Hsu North East Systems Associates Edward Sayre Plexus Joseph Socha Politechnico de Torino Igor Stievano Qlogic Larry Barnes Sintecs BV Hans Klos, Bob te Nijenhuis SiQual (Rob Hinz) Sun Microsystems Tim Coyle* Via Technologies (Weber Chuang) Xilinx Susan Wu In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode July 18, 2003 (916) 356-2663 2 381-4012 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum, and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Michael Mirmak and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ----------------------------------- INTRODUCTIONS AND MEETING QUORUM The IBIS Summit Meeting was held in Marlborough, Massachusetts at the Western Royal Plaza Hotel in conjunction with the DesignCon East Conference (DesignCon East 2003). The summit was co-sponsored by IBIS and Signal Integrity Software (SiSoft). About 18 people representing 9 organizations attended, including 5 people who attended via teleconference. The notes below capture some of the content and discussions. The meeting presentations and other documents are uploaded at: http://www.eda.org/pub/ibis/summits/jun03b/ Michael Mirmak opened the meeting and asked everyone in the room and on the teleconference bridge to introduce themselves. The group was well-attended by semiconductor vendors and model providers, EDA tool vendors and users of IBIS models. Michael thanked Signal Integrity Software (SiSoft) for their logistical support on-site. Finally, Michael thanked the presenters and participants for attending. Michael asked if there were any new issues or discussion items to put on the agenda. No issues were raised. PRESENTATIONS AND DISCUSSION TOPICS The rest of the meeting consisted of presentations and discussions. These notes capture some of the content and discussion. More details are available in the documents uploaded to the location noted above. STATE OF IBIS REPORT Michael Mirmak, Intel Corporation Michael opened the presentations with a summary of the summit agenda, a look back at the previous year, and a look ahead at the coming years' challenges. Michael noted that IBIS 3.2 is truly an international standard, as evidenced by European and Japanese interest, and that, despite the weak economy, the IBIS Open forum membership remained constant at 25 paid members. The organization remains financially healthy. Significant events this year included the passage of IBIS 4.0, the adoption of multi-lingual modeling, and the introduction of the Interconnect Modeling (ICM) specification for review by the forum. The biggest challenges for the coming year include enabling the future roadmap by passing IBIS 4.1 and adopting the ICM Specification. In addition, Michael described the need for an updated IBIS cookbook and for providing AMS modeling guidance to the industry. The IBIS Open Forum must also continue to work to improve model quality. Michael would also like to continue to track European EMC/EMI developments and determine the need for XML-based parsers. Finally, Michael offered his thanks to outgoing Chair Stephen Peters, the officers and other members of the organization for their support and help during the past year. IBIS QUALITY COMMITTEE UPDATE Kim Helliwell, Apple Computer and Barry Katz, Signal Integrity Software (SiSoft) Barry began his presentation by noting that, as cycle times decrease and edge rates increase, quality models are becoming more important. On recent accomplishments, the committee has completed review of seven of the 10 quality document sections. In addition, BUG 71 dealing with non-monotonic error due to individual I-V table checking has been passed. Barry noted that this was the most common warning from the parser, and with the parser now checking summed tables this warning will now have meaning. Barry reviewed the IBIS quality levels, noting that for a model to be valid at a level then it must have passed all previous levels. Regarding future items, Barry noted that there are 3 documents left to review (Vt curves and ramps, model correlation, and possible errors). Lynne Green will be compiling the sections into the final documentation. All documents will be correlated to the Quality Spreadsheet, forming a complete data set that developers and users can use for guidance in creation and evaluation of models. The final step after the documents are compiled and the checklist updated is to present the entire set to the Open Forum for approval. In response to a question, Barry mentioned that the committee plans to have this effort completed for review in time for the IBIS East summit meeting in October, 2003. Finally, Barry mentioned that the committee is interested in feedback on the document, even on the chapters that have not been completed. For additional information on the quality committee and to be included on the mailing list send mail to ibis-quality@freelist.org. The IBIS quality committee web site is available on the IBIS web page or at http://www.sisoft.com/ibis-quality IBIS INTERCONNECT MODELING SPECIFICATION (ICM) STATUS Michael Mirmak, Intel Corp Michael stated that the purpose of the IBIS Interconnect Modeling Specification (ICM specification) is to establish a human-readable standard format for exchanging interconnect modeling data. At a high level, the specification uses a two part format. The first part describes the model in terms of a 'section', with sections either joined in a tree arrangement according to implicit connections or in a nodal arrangement with explicitly described nodes. The second part of an ICM file supplies the electrical data for each section. Electrical data is in the form of either RLGC matrices or S-parameters. Michael noted that since September, 2002 over 63 issues have been formally logged. Most were editorial changes, but there were also some technical limitations and clarifications added. RLGC and S-parameter sections are not permitted within the same model. S-parameter data is only to be used with the [Nodal Path Description] keyword. Michael noted that the draft 1.0 specification was officially introduced at the May 30, 2003 meeting and a parser is in development. Michael asked for example models from the summit participants. Some technical advancements have been proposed for future revisions. One suggestion would permit mixing RLGC and S-parameter data within a single model description. Requests have also been made to include support for frequency dependent RLGC matrices. Enhancements and BUGS will be handled by a process similar to the existing BIRD process for the IBIS specification. For the longer term, suggestions have been made that explicit links between IBIS and ICM be made in one or both specifications. At present, tools are implicitly assumed to handle the use of ICM models as package data for IBIS models. A larger issue involves Touchstone(R) support for mixed-mode S-parameters. At present, Touchstone(R) is understood to support only standard single-ended S11, S12, etc. S-parameters. While the format can be used to distribute mixed-mode data (SDD12, SCD22, etc.), the specification includes no guidance for users or tools for interpreting the placement of the data points in a standard way. Feedback from participants, including Scott McMorrow, suggested that single-ended data was more than adequate for complete modeling of interconnects. Finally, Michael mentioned that to best support and encourage ICM usage, a cookbook is needed. A VHDL-AMS BUFFER MODEL USING IBIS V3.2 DATA Arpad Muranyi, Intel Corp. and Luca Giacotto, Université Joseph Fourier Arpad stated that the motivation for the presentation was to develop algorithms for simulating a basic I/O buffer model IBIS description using VHDL-AMS. Source code for this effort will be made freely available to anyone interested. Arpad noted that his presentation was not intended as a tutorial on the VHDL-AMS language. Arpad first presented a standard IBIS I/O model with four IV curves (pullup, pulldown, clamps) and Vt tables that describe switching. Arpad then introduced the classic equations which define the Vt and IV curve relationship, where the IV curves scale the Vt curves through coefficients called K factors (here, Kpu and Kpd for the pullup and pulldown factors, respectively). Arpad noted that Kpu and Kpd are assumed to be identical which may not be accurate in all cases. Arpad then went on to show the equations as implemented in VHDL-AMS code, where the two equations are solved to find the value of K. The equations are placed into a for loop, and K is resolved for each point on the pullup or pulldown curve. Arpad noted that the K values are calculated and stored from the model data when the simulator is initialized, not at run time. Arpad showed results comparing HSPICE B-element and AMS implementation results to data from the source transistor model. In general, the B-element and AMS curves matched closely, but were not identical. Then he presented a slightly different version of the code with separate structures defining the pullup, pulldown and clamp behaviors. The top-level code contained only the concurrent statements of the digital logic and transistors. Arpad then went on to explain how to solve an existing problem first noted when creating models for DDR memory interfaces. These models connect their terminations to VCC/2 when used, but the model is extracted with fixture voltages of VCC and GND. The best approach to using this data in these cases is that, while some simulators can only use two Vt tables at a time, different sets of Vt tables may be used at different times or depending on the model's initial conditions. Arpad described a four-curve data set, with fixture voltages set to 0, 1/3*Vcc, 2/3*Vcc and Vcc. With this set of waveforms, the AMS implementation overlays transistor level model results across the entire run time. Arpad noted that this approach still assumes that all Vt tables have the same R_fixture, which generally matches the target system impedance. Arpad's files are available on the IBIS web site. IBIS MODELS AT 1.25 GHZ AND BEYOND Bob Haller, Barry Katz, Kevin Fisher, Signal Integrity Software (SiSoft) Bob began by summarizing high speed design challenges that face signal integrity engineers today. They include, but are not limited to, interconnect (etch, packages and connectors), return paths, and high speed links. A frequently asked question is, "can IBIS be utilized?" The answer is a resounding yes! Bob reviewed LVDS (Low Voltage Differential Signaling) and some of the advantages it provides (high signaling speeds, lower voltage swing, less power consumption, less susceptibility to noise and reduced EMI. Bob then reviewed challenges creating IBIS models at 1.25 GHz and beyond. IBIS was originally designed to be single-ended and IV curves show current as a function of voltage on a single pad. In contrast, the current of an LVDS buffer is dependent on voltage at both pads and the common mode voltage. Bob walked through the process he uses to extract and generate LVDS IBIS models and cautioned that models are generated under specific operating, termination, and topology conditions. Often times these models are only accurate under the same conditions as the data was taken. He presented waveforms demonstrating excellent correlation between HSPICE and the IBIS model created and summarized the issues a model maker or user may encounter. He demonstrated this by showing the effect I/O voltage (VDDQ) has on the IBIS model. There was a discussion of modeling on-die termination that was tabled until later in the day, when on-die termination was going to be addressed. Finally, Bob reiterated that we can generate models for 1.25 GHz and beyond, but it takes significant effort and attention to detail. Improper use of, or improper building of models can and will lead to inaccurate results. IBIS 4.1 STATUS AND UPDATE Lynne Green, Cadence Design Systems Lynne began her presentation by noting that IBIS 4.0 was approved in July, 2002 and a parser is expected in the third quarter of 2003. IBIS 4.1 will include five additional BIRDs, including the major addition of multi-lingual modeling support. Lynne also noted that there is one outstanding BIRD that will probably not be included in IBIS 4.1. The remaining BIRDS to be included in IBIS 4.1 address several different issues. Improved support for differential buffers is addressed through BIRD 77. BIRD 80 added ext_ref as a new [Pin Mapping] column, helping to drive adoption of BIRD 78 to extend the line length limit to 120 characters. Finally, BIRD 81 clarifies [Series Pin Mapping] and series model usage. The next step in IBIS specification development is presentation of the draft version of IBIS 4.1 to the Open Forum for an approval vote. Once the specification is approved, a parser is written and any issues which arise from parser development are folded into IBIS 4.2 (which may include an EMC specification as defined by BIRD 74). When the IBIS 4.2 parser is stable, the specification will be presented to ANSI/EIA for approval through a formal letter ballot. IBIS ALGORITHMS REVISITED Bob Ross, Teraspeed Consulting Group Bob stated that his slides were part of a larger presentation given at the IEEE SPI Conference in Siena, Italy earlier this year. Bob noted that, early on, IBIS tools settled on a data-processing algorithm involving two waveforms, but there are other algorithms possible. These include using multiple tables with dynamic interpolation and modeling the transistors themselves as was done for the Japanese IMIC specification. Recently, radial base functions have also been considered. Bob first explained a very simple algorithm using only ramp data and assuming a 5 volt linear device driving into a 50 ohm resistive load. Additional variations, including Norton and Thevenin linear transitions plus table multipliers, were addressed along with a comparison to actual waveforms. Bob showed how two waveforms were required to get independent K values for IBIS pullup and pulldown data. More advanced simulation techniques must handle generalized loading cases, rather than loads which are purely resistive. Bob used a SPICE netlist to address the problem, incorporating two models in a feedback loop of an operational amplifier, where the amplifier itself drove the scaling or K table values. The input of the amplifier, being connected to the output node, would then converge on an appropriate solution for the load used. Finally, Bob addressed overclocking IBIS buffers, where IBIS models are driven in simulation over shorter periods than allowed by the length of the Vt waveforms. Unfortunately, no immediate solution to this problem is currently available. AN ALGORITHM TO MODEL OVER-CLOCKING MORE ACCURATELY Arpad Muranyi, Intel Corp. In addition to his scheduled presentations, Arpad provided an ad-hoc set of slides addressing the driver overclocking problem. Using several image overlays, Arpad demonstrated that overclocked buffers show a relatively constant delay between pulldown turning off and pullup turning on, and vice-versa. Arpad proposed that this delay could be characterized and included with other IBIS data as a parameter. MODELING ON-DIE TERMINATIONS IN IBIS (WITHOUT DOUBLE COUNTING) Arpad Muranyi, Intel Corp. Arpad began his presentation by noting some of the more advanced design features now commonly available, including dynamic clamps, staged buffers, kicker circuits and the like. While many of these features may be difficult to model without intimate knowledge of the buffer design, a general rule of thumb is that any design aspect which is static should be represented through the IBIS clamp tables. Users and model makers observing this rule for terminations should be careful to use the appropriate rail for correct power and ground bounce simulations. Most especially, double counting of these termination features should be avoided whenever possible. Arpad classified the types of termination as series, parallel or switched parallel. Series termination does not require any special analysis for inclusion in IBIS as it will naturally be included in the IV curve shapes. Parallel termination behaviors should be placed in clamp tables by sweeping the voltage on the pad from -Vcc to 2*Vcc, both using ground referencing and Vcc referencing. By finding the curve which passes through the origin, one can find the curve set most appropriate in which to include the resistor. This curve will be cut at Vcc, while the other will be cut at ground. The curve without the resistor can then be normalized or shifted to pass through the IV origin. Both curves can then be extrapolated to 2*Vcc. Switch parallel terminations are commonly implemented by leaving either the pullup or pulldown active when the device receives. In this case, normal I/O IV curves may be created and the appropriate pullup or pulldown curve may be copied to a [Submodel] and renamed to be a dynamic, non-driving clamp. Example IBIS text for this implementation was provided. Finally, Arpad addressed the case where both pullup and pulldown terminations are present in a design. The model maker in this case cannot be sure how to determine the value of each termination separately when only the Thevenin equivalent can be observed. Lynne Green and Bob Ross suggested that analysis of the slopes can be used to help determine where non-linear resistive termination data can be included. ON-DIE TERMINATION COMMENTS Bob Ross, Teraspeed Consulting Group Bob commented that he investigated the on-die termination problem with parallel terminators and composite I-V extraction. After several false starts, Bob stated that more information is required. He illustrated a case where a straight line I-V table can be modeled as two linear resistors or as two quadratic resistors. The second case mimics the situation that a MOSFET is used. Bob created a quadratic solution that had 0 slope at one voltage and a prescribed slope at the other. The combination produced a linear I-V table. Bob concluded that either more constraints are necessary, or preferably, a separate power or ground current extraction should be used. Bob had attempted deriving a quadratic interpolation algorithm, but the equations were not independent. OTHER DISCUSSIONS AND AD HOC PRESENTATIONS Todd Westerhoff added some humor with a closing "IBIS prayer." Our Founder, who art in California, Arpad be thy name. Thy mastery IBIS, thy will be modeled, industry-wide, as it is at Intel. Give us this day a better spec. Forgive us our S.W.A.G.'s, as we forgive those who S.W.A.G. against us. And lead us not unto error, but deliver us from non-convergence. For thine are The Research, The Algorithms and The Standard forever and ever. AMEN CONCLUDING ITEMS Barry Katz thanked the presenters for the great and informative presentations. After reminding the participants regarding the next teleconference meeting, Barry closed the IBIS Summit Meeting. NEXT MEETING: The next Open Forum meeting will be held on Friday, July 18, 2003 from 8:00 AM to 10:00 AM Pacific time. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046 michael.mirmak@intel.com Senior Analog Engineer, Intel Corporation M/S FM6-45 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 451-1871 lgreen@cadence.com Senior Modeling Engineer, Cadence Design Systems 320 120th Ave NE, Suite B-103, Bellevue, WA 98005-3016 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 1-711 Boise, ID 83707-0006 LIBRARIAN: Roy Leventhal (847) 590-9398 roy.leventhal@ieee.org Consultant, Leventhal Design and Communications 1924 North Burke Drive Arlington Heights, Illinois 60004 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008 John_angulo@mentor.com Development Engineer, Mentor Graphics 14715 N.E. 95th Street, Suite 200 Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: majordomo@eda.org In the body, for the IBIS Open Forum Reflector: subscribe ibis In the body, for the IBIS Users' Group Reflector: subscribe ibis-users Help and other commands: help ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eigroup.org/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous.