DATE: 06/16/04 SUBJECT: June 8, 2004 EIA IBIS Open Forum Summit Minutes VOTING MEMBERS AND 2004 PARTICIPANTS Cadence Design Systems C. Kumar, Patrick dos Santos, Lance Wang Cisco Systems Sergio Camerlo, Syed Huq*, Mike LaBonte, Stan Penner, Todd Westerhoff Hitachi ULSI Systems Kazuyoshi Shoji* Intel Corporation David Keates, Peter T. Larsen Wilson Leung, Michael Mirmak*, Arpad Muranyi*, Steve Peterson Matsushita (Panasonic) Atsuji Ito* Mentor Graphics John Angulo*, Guy de Burgh, Weston Beal, Ian Dodd*, Gary Pratt, Eric Rongere, Stephane Rousseau Micron Technology Paul Gregory, Randy Wolff NEC Electric Corporation Takeshi Watanabe* Samtec Otto Bennig* Siemens AG Eckhard Lenski, Manfred Maurer Siemens Medical (Acuson) David Lieby Signal Integrity Software Robert Haller, Barry Katz Sigrity Raymond Chen*, Jiayuan Fang Synopsys Warren Wong*. Edmund Cheng* Texas Instruments Jean Claude Perrin, Hector Torres Teraspeed Consulting Group Tom Dagostino, Scott McMorrow, Bob Ross* Time Domain Analysis Systems Steve Corey Zuken (& Incases) Ralf Bruening, Caroline Legendre, Laetitia Simonian OTHER PARTICIPANTS IN 2004: Actel Prabhu Mohan* Alcatel Jean-Pierre Bouthemy Ansoft Corporation Hank Campbell*, Eric Bracken Apache Design Yu Liu Applied Simulation Technology Norio Matsui* Bayside Design Daniel Lambalot, Kevin Roselle Bee Technologies Tsuyoshi Horigome* Conexant Garry Felker Cortina Systems Robert Badal EADS Olivier Maurice Edality Rob te Nijenhuis EFM Ekkehard Miersch Extreme Networks Lin Shen Fraunhofer IZM Ege Engin GEIA (Chris Denham) Green Streak Programs Lynne Green* Independent Kim Helliwell, Jon Powell INSA Etienne Sicard Interface Technologies Dan Waterloo* LSI Logic Frank Gasparik Netlogic Microsystems Eric Hsu North Carolina State Univ. Paul Franzon*, Ambrish Varma* North East Systems Associates Edward Sayre Northrup Grumman Dan Crain*, Adrianna Zammit* Politecnico di Torino Igor Stievano Samsung Il Seong Silverback Systems Gil Gafni Sintecs BV Hans Klos In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode June 25, 2004 1-916-356-2663 4 844-9148 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- INTRODUCTIONS AND MEETING QUORUM The IBIS Open Forum Summit was held in San Diego, California at the Manchester Grand Hyatt during the 2004 Design Automation Conference (DAC). 23 people representing 19 organizations attended. The notes below capture some of the content and discussions. The meeting presentations and other documents are uploaded at: http://www.ibis-information.org/summits/jun04/ Michael Mirmak opened the meeting. Michael thanked John Angulo for his logistical support in obtaining a room and making luncheon and refreshment arrangements. He also singled out Lynne Green for her assistance with calls for papers and setting the agenda. Finally, Michael thanked the presenters and participants for attending. Michael asked everyone in the room to introduce themselves. The group was well-attended by a cross-section of the IBIS community, including semiconductor vendors, service providers, EDA tool vendors, and IBIS users. Michael asked if there were any new issues or discussion items to add to the agenda. No issues were raised. PRESENTATIONS AND DISCUSSION TOPICS The rest of the meeting consisted of presentations and discussions. These notes capture some of the content and discussion. More details are available in the documents uploaded to the location noted above. IBIS CHAIR'S REPORT AND ROADMAP UPDATE Michael Mirmak, Intel Corporation Michael Mirmak summarized the current state of the IBIS Open Forum and its activities. IBIS 4.1 and ICM are becoming increasingly visible in the industry, especially with the help of JEITA and the April EDN Japan magazine article on consumer electronics and IBIS. Updates to IBIS 4.1 and ICM are being actively considered by the Futures Subcommittee, while outlines for updated IBIS and ICM cookbooks have been completed by the Cookbook Subcommittee. The IBIS web presence is being polished through a new index of summit presentations, in addition to the web overhaul being planned by webmaster Syed Huq. The presentation continued with a summary of significant "storms" in the organization's immediate future. Membership renewals are lagging, with at least eight (8) needed to ensure financial solvency by the end of the year. Additionally, more Golden Parser license purchases are needed to ensure that an IBIS 4.1 parser will be available for model development this year. As 4.0 purchasers receive free upgrades, the IBIS 4.1 parser must be financed entirely through new license purchases. At least six (6) new purchases are needed to guarantee completion of the parser, from estimated development costs. Michael also presented an updated timeline for IBIS development. While the ICM cookbook will be issued later than originally scheduled, proposals for ICM improvement, the updated IBIS parser and a draft IBIS 4.2 specification should all be completed as scheduled, assuming the above financial issues can be resolved. The E-Roadshow program has been placed on hold, pending commitments for web seminar support from members. The costs of live presentation teleconferences are too large for the IBIS Open Forum to absorb at this time. Finally, Michael thanked the current officers -- Lynne Green, Syed Huq, Randy Wolff, Roy Leventhal and John Angulo -- plus longtime advisor Bob Ross, for their help in "making IBIS happen" over the past year. Several participants inquired about the difference between parser payments and membership dues. Additionally, some participants asked for information on the allocation of IBIS funds. Michael responded with a brief summary of major IBIS expenditures. Parser license fees are spent only on parser development and not on other purposes. Membership fees are used to support the regular operation of the IBIS Open Forum, including paying for the DAC Summit and other summit expenses, reproduction fees and the like. Most of the membership dues are paid in turn to the GEIA, which provides accounting and legal services to the Open Forum and supports the ANSI balloting process. THE IBIS MODEL REVIEW COMMITTEE Lynne Green, Green Streak Programs Lynne Green summarized the process used by the IBIS Model Review Committee to check models given to them for comment. The Committee consists of representatives from major EDA tool vendors who provide their feedback directly to the model author. Confidentiality is assured, and device manufacturers are discouraged from seeking a position on the Committee. According to Lynne, 90% of the buffer models received contain significant problems and typical feedback to the author consists of 2-3 pages of comments. Typical checks include running the golden parser, graphical analysis of the data tables to look for monotonicity, V-t settling and avoidance of clamp double-counting. Additionally, "sanity" checks on values such as temperature help ensure realism in the resulting simulations. In many cases, simple visual checks -- do the waveforms pass through the correct voltages? are there sufficient data points to describe curves smoothly? -- are enough to identify most issues. Lynne provided a step-by-step analysis of a poorly written model to illustrate many common errors. Lynne also reviewed the relationship between the IBIS Quality Committee documents and the Review Committee procedure. Several participants in the Review Committee also attend Quality Committee meetings and apply the Quality checklists in their review work. Finally, Lynne thanked the Review Committee for their efforts. ELECTION OF OFFICERS Michael Mirmak announced the positions and nominees. Some positions featured several nominees. Without dissent, the following candidates were elected by the voting membership as officers for 2004-2005: Chair: Michael Mirmak Vice-Chair: Syed Huq Secretary: Randy Wolff Postmaster: Bob Ross Webmaster: Syed Huq Librarian: Lance Wang Michael thanked the outgoing officers and congratulated the new officers. Michael presented some commemorative items to the 2003-2004 board members, and Lynne Green presented one to Michael. Also, Bob Ross passed out some IBIS picture coasters to participants as a token of appreciation. SIMULTANEOUS SWITCHING NOISE IN IBIS MODELS Ambrish Varma, North Carolina State University Ambrish Varma presented a brief comparison of IBIS and SPICE transistor descriptions of simultaneously switching buffer noise. By using the S2IBIS3 program, Ambrish converted a SPICE description of a buffer into IBIS format, then he ran the IBIS buffer in a circuit topology using Synopsys HSPICE(R). Pin parasitics were attached to the power and ground rails, and four buffers were driven together, with three switching simultaneously. The results showed that IBIS consistently overpredicted the maximum peak current generated by the simultaneously switching buffers. Using a spline functions in a finite difference approximation, it may be possible to better model the peak current, if the splines can be fitted to buffer design data. The spline code, generated by Georgia Institute of Technology, creates a non-linear relation between static and dynamic buffer behaviors for output current and voltage. The static values are derived from DC sweeps. The actual spline function is implemented in a macromodel with voltage- and current-controlled current sources. In general, the spline method resulted in a 50% improvement in the error vs. the transistor model over IBIS. Unfortunately, the spline function generation is not automated, is slower than IBIS, and is difficult to implement (The Math Works' MATLAB(R) was used to generate the equations). Ambrish posed the question to participants whether a 50% improvement over IBIS was worth a potentially increased simulation time. Bob Ross noted that most users would not accept slowdowns in simulation for a behavioral model, as significant computation time makes a transistor-level model more attractive. Norio Matsui asked whether loading changes have been taken into account, as ground bounce may change with loading conditions. Ambrish indicated that this was not varied in the spline experiments. Arpad Muranyi suggested that the Synopsys HSPICE(R) scaling coefficients for the IBIS B-element be used to examine and confirm some of the effects that the spline fitting predicted, but using IBIS data. Additionally, John Angulo noted that, as speeds change when rail voltages vary, the IBIS table data might be scaled with supply bounce to increase accuracy. I-T TABLES AND BIRD42.3 REVISITED Bob Ross, Teraspeed Consulting Group Bob Ross summarized the best known methods for simulating power delivery circuits under IBIS, based on previous summit presentations. Raymond Chen had previously advocated using a Cdie parameter, between the power and ground rails, to improve modeling of simultaneously switching buffer noise. In 2000, Bernhard Unger proposed modeling voltage rail collapse by adding a prestage capacitance (similar to Cdie) and additional k-coefficient data to describe pulldown and pullup behavior as the rail voltage varies. In 2002, Sebastien Calvet described emissions from the core, outside of IBIS, through ICEM RLC circuits; these can also be described under IBIS 4.1 using the SPICE multi-lingual extension. Finally, BIRD 42.3 in 1997 proposed adding additional pullup and pulldown current vs. time tables to ensure that the current distribution, including crowbar, was adequately accounted for in addition to output current flow. Bob then described some of the problems with this approach. First, internal terminations, clamps and distributed capacitances may have their own current flows, apart from pullup and pulldown reference currents. These would have to be accounted for or assumed by the tools to provide truly accurate results. Additionally, the current distributions for keywords such as [Submodel] and [Driver Schedule] would need additional clarification in the specification. Bob suggested an alternate description format, which features delta voltage and delta current tables; this does not necessarily eliminate the problems noted for the I-T tables of BIRD42.3. Finally, Bob presented the methods and issues possible for data extraction of I-T tables. A SPICE circuit would be the most likely method of obtaining the table data for pre-layout analysis. However, the best fixture loading and voltages are not known a priori, nor is the accounting used for the pre-drivers clear. Measurement is even more difficult. As package effects are included, unrelated circuits might cause measurement distortions and some buffers may be difficult to shut off for the measurement. Package modeling of the supply rail is also not explicitly addressed under IBIS. Based on all this, Bob expressed his doubt that I-T tables can adequately solve the buffer or core power delivery issues now being raised in the industry. CASE STUDY OF IBIS 4.1 BY JEITA EDA-WG Atsuji Ito, Panasonic Takeshi Watanabe, NEC Norio Matsui, Applied Simulation Technology Atsuji Ito presented a brief summary of JEITA (Japan Electronics and Information Technology Industries Association) and its EDA Working Group. The Working Group was reorganized in January 2004 after changing its focus from passive components to both passive and active device modeling. Its objectives now are to improve modeling for digital consumer electronics -- including cellular telephones, LCD televisions, etc. -- and also automotive electronics. This entails coverage of a very large scope of electronics industry activities, including connectors, PCBs, RF modules, ICs, packages and even crystals, in EMI, RF, and signal integrity contexts. The Working Group's membership includes many companies across all these industry areas. Norio Matsui discussed the Working Group's conclusions after its investigation of IBIS 4.1 and ICM 1.0. Berkeley SPICE can be used with IBIS 4.1 to describe all the major applications of interest to JEITA: ASIC EMI, power semiconductors and operational amplifiers, packages and PCBs, passive components, and cable assemblies. However, semiconductor intellectual property would not be protected in this case. IBIS 3.2, by contrast, has applications only for buffers and limited descriptions of packages, PCBs and passives. ICM has applications for packages, connectors, PCBs and passives, but was not seen by JEITA to model discrete components. Arpad Muranyi suggested that IBIS 3.2 has several keywords to enable discrete component descriptions, and that S-parameter descriptions could cover discretes just as well as more complicated circuits. Dr. Matsui expressed concern that there were no direct links between IBIS and ICM. Several participants pointed out that the Futures Subcommittee is developing these links for a future IBIS release (4.2). However, such links could be handled at the tool level, without explicit connections between the two specifications. Dr. Matsui suggested that IBIS 4.1 should have application to packages, passives and connectors. However, there do not appear to be Berkeley SPICE constructs for S-parameters or lossy coupled transmission lines. Proper methods for AMS modeling for these applications is not yet clear. Additionally, there is significant interest in Japan in using IMIC (table-based SPICE transistor models) in combination with IBIS. At present, there is no direct support for IMIC in IBIS. Arpad suggested that IMIC algorithms could be developed in AMS under IBIS 4.1, so that IMIC data could be processed directly. Paul Franzon expressed concern that, while IMIC hides transistor process information, the netlist description is still open to anyone. Dr. Matsui stated that higher level macromodels enable transistor descriptions through tables without compromising specific netlist information. Ian Dodd noted that, while [External Circuit] should allow most of what was being proposed under IBIS 4.1, EDA tools today still need measurement information for the buffer which is not provided under [External Circuit]. Takeshi Watanabe described the specific application of behavioral data toward EMI simulation. Using a standard method developed by the IEC, a magnetic probe can be used to measure the current and emissions of an LSI-based PCB design. In simulation, the LSI topology would be modeled using I/O buffer and clock models plus package and PCB models which include power and ground plane descriptions. These models must include both time and frequency domain effects. Correlation can be quite good when using a combination IBIS 3.2 and IMIC description of the LSI devices and interconnects. Such an approach could be unified under IBIS 4.1, assuming a SPICE LEVEL=3 description was linked through the multi-lingual extensions, after being converted from another SPICE description. CASE STUDY OF IBIS 4.1 BY JEITA EDA-WG PART-2 Norio Matsui, Applied Simulation Technology Atsuji Ito, Panasonic Takeshi Watanabe, NEC Dr. Matsui continued with Part II of the presentation, summarizing several questions about IBIS 4.1 and its applications. First, IBIS 4.1 does not enable encryption or other means of hiding SPICE circuit details. There are concerns in the Working Group that AMS may not be as accurate as a SPICE-level description. IMIC is seen as an appropriate option, but it is not available under IBIS 4.1. Arpad reiterated his suggestion that IMIC algorithms can be described under AMS. Michael Mirmak added that SPICE-level solutions are simply behavioral models by another name. SPICE may include many details which are not needed for all applications, and are not guaranteed to be accurate themselves merely because they appear complete or complex. AMS models can be demonstrated just as accurate as SPICE buffer models, but require more model author expertise to generate correctly than SPICE models. Potential applications of IBIS, AMS and SPICE include mixing of languages, single pins with multiple output models connected, and systems-in-packages. Participants responded that all three are possible using [Circuit Call] and [External Circuit]. Further, multiple outputs, for example using pre-emphasis and de-emphasis, can be implemented using [External Model] as Arpad has demonstrated, if the complete circuit is described in the AMS code. Related to this is whether S-parameters and RLGC matrices can be used for packaging if only a few signals are needed for simulation. A complete S-parameter model may be supplied for the package, but no easy method exists for extracting the behaviors of just a few signals. Ian Dodd mentioned that some procedures exist to perform these extractions, but many are proprietary. Power and ground islands are becoming more prevalent in Working Group designs, as consumer devices become smaller. Participants agreed that non-ideal power and ground modeling is critical, but this awaits settling of the buffer-level power delivery modeling issues before it can be incorporated in IBIS. ICM can be used, in the short term, to describe some plane behaviors. Partial differential equations are of use, especially for lossy transmission lines, but do not yet have a direct keyword in either AMS language. This will require more research by the IBIS Open Forum and potentially requests to the AMS standards bodies. Accuracy and quality documents are also in high demand, but do not appear to be available yet. Michael took the AR to provide these to the Working Group. ICM and terminators was mentioned as a demanded application. IBIS EBD and ICM can all describe these, either with nodal descriptions in RLGC format (with simple R-only matrices for resistors, etc.) or passive S-parameters. Active S-parameters are not explicitly prohibited by the specification, but would be difficult to check for errors or to use in today's simulation tools. Finally, Norio inquired about IBIS 4.1 application in the frequency domain, especially for Rac and Rdc. This is possible using AMS and even IBIS 3.2, according to the participants, depending on the detail level required. Norio also asked about AMS model generation from SPICE details, as S2IBIS3 generates IBIS data from SPICE. Lynne Green mentioned that at least one DAC exhibitor was offering just such a conversion tool. I-V CURVE LINEARITY AND BUFFER IMPEDANCE Arpad Muranyi, Intel Corp. Arpad Muranyi summarized the need for I-V curve linearity for buffer modeling. New interfaces, such as DDR3 and PCI Express(R), operate in the current mode, where the I-V curves are assumed to be flat or at least highly linear. In many cases, drivers are described using Ron without a more comprehensive specification for the I-V curve shape or bounds. Arpad compared the calculated resistance of a pulldown curve with the first derivative of the resistance. By overlaying the waveforms, the derivative is clearly not equal to the resistance at most voltage points which might be used for comparison. This becomes a problem for AC (frequency domain) simulation, where the derivative of the I-V curve will be used; in cases where an R-V curve is present the actual R value from the table would be used. These would not be equal and would therefore give different results, possibly mispredicting resonances. No effect would be noted in the time domain. Arpad went on to suggest that the actual reflection coefficient for the buffer is the most appropriate parameter to use for resonance prediction. This value can be obtained through the Zac of the buffer and the impedance of the transmission line connected to the buffer. The Zac of buffers in experiments run by Arpad show significant frequency dependence. By further experimentation, Arpad suggests that the pre-driver impedance is coupled to the output pad through a Miller capacitance. All of these effects therefore appear in the resulting Zac of the buffer. These results correlate well with predictions made in BIRD79. Bob Ross commented that care should be taken when obtaining the real value of the buffer impedance. Real(Vac)/Real(Iac) is not the same as Real (Vac/Iac), assuming that both Vac and Iac are complex quantities. DREAMWEAVERMX(TM) AND FLASHMX(TM) FOR IBIS WEBPAGE Syed Huq, Cisco Systems Syed Huq reviewed the history of the IBIS web presence, noting that the site was first posted in 1995. The GEIA controls the official site, with a second site, containing most of our documents, located on a separate server at eda.org (we have change access at eda.org). Syed proposed that several industry standard tools from Macromedia be used to revise and update the web site, in order to ease maintenance and make the site more useful to visitors. The tools support such common web enhancements as layers (under CSS, the Cascading Style Sheet format), standard templates, databases, testing under various browsers, forms, and link checking. FlashMX(TM) enhancements would enable animation, scalable graphics and dynamic text, which could be used for news and announcements. As the GEIA already uses the ColdFusion(TM) tool, migration should be easy. Syed also provided a brief demonstration of DreamWeaverMX(TM) and showed how a revised IBIS web site would look. Features included pulldown menus and visitor polling. Participants suggested that forms for joining the IBIS reflectors be posted on the updated site. Syed recommended that IBIS participants provide him with feedback on useful enhancements. OPEN DISCUSSION Syed Huq raised the issue of I-T tables and BIRD42.3. In brief, one of the most critical issues facing the design community is in predicting core current spikes. Many are looking to the IBIS Open Forum to develop a solution or means to model these behaviors. As a first attempt or test, buffer-level power delivery modeling is being proposed through a reactivated BIRD42.3. Key learnings from this effort can be applied to solving the core issues. Bob Ross again expressed skepticism that a buffer-level approach could be adapted to core-level applications. Instead, he recommended using buffer switching noise as part of an overall power solution, rather than as a "stepping stone." As IBIS is now conservative in its power estimates, it has some use to designers. Syed mentioned that, although IBIS is useful, most designers use SPICE circuit simulation for simultaneous switching analysis. Lynne Green inquired whether designers are actually seeing real-world failures due to core current issues. Syed confirmed that such issues do exist. Arpad Muranyi suggested that a VHDL-AMS or Verilog-AMS solution could be found, once the interactions between the core and buffer are defined; IBIS 4.1 is not limited to describing only buffer-level behavior. Michael Mirmak called for volunteers to investigate these issues further. Lynne and Arpad expressed willingness to start developing an AMS-based solution. Syed volunteered to work with them and also to begin examining how combination die/buffer-level power behavior might be described. CONCLUDING ITEMS Michael Mirmak again thanked the presenters, supporters, and sponsors for their help and support in making the Summit a success. After reminding the participants regarding the next Open Forum teleconference, Michael closed the IBIS Summit Meeting. NEXT MEETING The next Open Forum teleconference has been scheduled for June 25, 2004 from 8:00 AM to 10:00 AM US Pacific Daylight Time. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046 michael.mirmak@intel.com Senior Analog Engineer, Intel Corporation FM6-45 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 1-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, CA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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