------------------------------------------------------------------ AGENDA, IBIS SUMMIT MEETING June 14, 2005 Anaheim Marriott 700 West Convention Way Anaheim, CA 92802-3483 Room: Gold Key I and II, Anaheim Marriott (check signs at site) Co-sponsors: IBIS committee, Mentor Graphics, Cadence Design Systems, ------------------------------------------------------------------ 8:00 AM Refreshments & Sign In 8:30 AM Introductions - Welcome to Summit - Introductions - Opens for Issues, Discussion Topics 8:45 AM IBIS Chair's Report and Roadmap Michael Mirmak, Intel Corporation 9:00 AM Library Modeling Project at Silicon Integration Initiative (Si2) Sumit Dasgupta, Si2. H. John Beatty, IBM 9:30 AM Power Integrity Proposal regarding BIRD95.5 Ken Willis, Cadence Design Systems 10:15 AM BREAK 10:30 AM Election of Officers 10:45 AM Multi-buffer simulation using BIRD95.5 Dr. Zhiping Yang, Cisco Systems, Inc. Ilyoung Park, Cisco Systems, Inc 11:15 AM Multi-Gigabit SerDes Simulation using IBISv4.1 (VHDL-AMS) Syed Huq, Cisco Systems, Inc. Ian Dodd, Mentor Graphics 12:00 PM LUNCH - Pre-registration required 1:00 PM IBIS 4.1 Macros for Simulator Independent Models Arpad Muranyi, Intel Corporation 1:30 PM Things you can learn from V-I curves Todd Westerhoff, Cisco Systems, Inc 2:00 PM Asian IBIS Summit Bob Ross, Teraspeed Consulting Group 2:15 PM Opens/Discussion 3:00 PM BREAK 4:45 PM Opens/Discussion 4:55 PM Concluding Items - Next Open Forum Meeting: June 24, 2005 5:00 PM End of IBIS Summit Meeting ------------------------------------------------------------------------ REGISTRATION People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below: Name: E-mail address: Company: Telephone: Please send registrations to shuq@cisco.com. ------------------------------------------------------------------------