DATE: 4/6/00 SUBJECT: 3/31/00 EIA IBIS Summit Meeting Minutes VOTING MEMBERS AND 2000 PARTICIPANTS LIST: 3Com Roy Leventhal Agilent (EEsof, etc.) Mark Chang Hewlett Packard Paul Gregory Applied Simulation Technology Raj Raghuram, Norio Matsui, Fred Ballesteri Avanti Nikolai Bannov Cadence Design Mike LaBonte, Todd Westerhoff, Ian Dodd, Donald Telian, Patrick Dos Santos* Cisco Systems Syed Huq, Irfan Elahi, John Fisher Compaq Bob Haller, Peter LaFlamme, Ron Bellomio, Shafier Rahman, Doug Burns Cypress (Rajesh Manapat) EMC Corporation (Fabrizio Zanella), Fairchild Semiconductor Craig Klem H.A.S. Electronics (Haruny Said) HyperLynx (& Pads Software) Matthew Flora, Kellee Crisafulli, Gene Garat, John Angulo, Al Davis, Lynne Green IBM Michael Cohen Incases Werner Rissiek* Innoveda (Viewlogic Systems) Chris Rokusek, Guy de Burgh, Jun Tian, Cary Mandel*, Brad Griffin*, (Jon Powell) Intel Corporation Stephen Peters, Arpad Muranyi, Will Hobbs, Richard Mellitz LSI Logic (Larry Barnes) Mentor Graphics (& Veribest) Bob Ross*, Tom Dagostino*, Malcolm Ash, Kim Owen, Jean Oudionot*, Sherif Hammad*, Hazam Hegazy* Mitsubishi Shahab Ahmed Molex Incorporated Gus Panella Motorola Ron Werner National Semiconductor Milt Schwartz North East Systems Associates Edward Sayre, Tony Sinker NEC (Hiroshi Matsumoto) Nortel Networks Steve Coe, Calvin Trowell, Hassan Ali Philips Semiconductor D.C. Sessions (& VLSI Technology) Quantic EMC (Mike Ventham) Siemens AG Bernhard Unger, Gerald Bannert* SiQual Scott McMorrow, Wis Macomson Texas Instruments Stephen Nolan, Ramzi Ammar, Mac McCaughey, Thomas Fisher*, Jean-Claude Perrin*, Jean-Yves Oberle* Time Domain Analysis Systems Dima Smolyansky, Steven Corey Via Technologies (Weber Chuang) OTHER PARTICIPANTS IN 2000: Actel Corp. Silvia Montoya Advansis Mikio Kiyono Aerospatiale Matra CCR Lionel Dreux*, Julien Boullie* Alcatel (Lannion, Bell) Daniel Peron*, Steven Criel* Brocade Communications Robert Badal EIA Cecilia Fleming Fraunhofer Instutute Michael Kurten* Jet Propulsion Lab John Treichlew Rockwell Collins Ron Hau Signals & Systems Engineering Tom Hawkins ST Micorelectronics Fabrice Boissiere*, Pierre Saintot* Sun Microsystems Victor Chang Thomson-CSF Savenrio Lerose*, Pascal Vaslin*, Thierry Zak*, Sylvie Lasserre* Transfer Hans Klos*, Wilco Hamhuis* Xilinx, Inc. Susan Wu In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as follows: Date Bridge Number Reservation # Passcode April 14, 2000 (916) 356-9200 8-97978 5851557 All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out 7 days before each Open Forum and meeting minutes out within 7 days after. When you call into the meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the reservation number and passcode. NOTE: "AR" = Action Required. -------------------------------- MINUTES ------------------------------------- INTRODUCTIONS The European IBIS Summit Meeting was held in Paris, France the day after the Design Automation and Testing in Europe conference (DATE 2000) at the Concorde La Fayette Hotel. Cadence Design, Incases Engineering, Innoveda (formerly Viewlogic Systems), Mentor Graphics served as co-sponsors. About 26 people representing 12 organizations participated. Bob Ross welcomed the participants and noted that questions and interactive discussion was encouraged. Everybody introduced himself. Semiconductor vendors, EDA vendors and users (along with an individual from a research institute) were all represented. (Also, thanks to Karine Loudet and Francoise Lindecker of Mentor Graphics for producing the posters and handling the administrative and registration details.) All of the presentations and meeting documentation will be uploaded at http://www.eda.org/pub/ibis/summits/mar00/ The notes below give some off the content and discussion. SIEMENS ICN I/O MODEL SPECIFICATION (Terms of Delivery for I/O Models of Digital Integrated Circuits V50004-Y1-T210-*-7625 Revision Feb.08.2000) Gerald Bannert, Siemens AG Gerald Bannert passed around the above draft specification. It includes material presented at previous European IBIS Summit meetings. Siemens prefers IBIS models. However, Gerald finds that IBIS Models from manufacturers are insufficient for Siemens needs for several reasons: They use older than Version 3.2 revisions of IBIS. Useful options are missing, and model quality is not good. Technical IBIS content and parameter definition in IBIS is insufficient, incorrect, or difficult to understand. Some additional parameters are needed for the internal Logical Design Rule Checker (LDRC) tool. The specification contents are: Part 1: Quality, references, data consistency, transaction complete. Part 2: Technical supplement/changes to IBIS Version 3.2 Part 3: Additional parameter requests. The specification is being reviewed internally and is also being distributed to major semiconductor vendors. Additions to the document are expected for improved accuracy, EMI, HF, and SSO. Vendors supplying the added information of Part 3 may become preferred vendors. Gerald then gave an overview outline of the content (summarized here): Superordinate, general and technical requirements for delivery (16 pages) General introductory and scope material Guarantee, model changes (MCN) validity for models tracking device changes General requirements for IBIS models - application, data consistency, availability and definition of typ, min, and max parameters for process, Tj, and Vcc Requirements for other formats (underway) Plus parameter requirements Annex 1 (27 pages) Technical definitions (e.g., overshoot, Vdiff) Limits of interest Measurement and simulation conditions (e.g., SSO, Tj, loads) IBIS points of table entries Siemens ICN options Annex 2 (18 pages) File structure and relationship of .ibs and .sie (for Siemens) Technical data definition (e.g., fail safe, Vsource, slew rate, I/O type Functional pin mapping (e.g., clock, data) Gerald discussed a number of these points. The IBIS Version 3.2 specification only gives general guidelines for entering typ, min, and max parameters. The Siemens document gives more detailed definitions. The typical model should have typical process conditions within +/- 0.5 sigma. The standard JEDEC voltages (12, 5, 3.3, 2.5, 1.8, 1.5, and 1.3) need to be specified. The typical junction temperature condition should correspond to about 40 degrees C ambient. The min and max process parameters should be approximately the 2.3 sigma points. The voltages should be +/- 5 percent. The junctions temperature range should be 0 degrees C to 110 degrees C. Some existing IBIS models from semiconductor vendors have too large of a range to be useful in real designs. Gerald elaborated on a needed Vdiff_max subparameter for differential pins and how they relate to S_overshoot and D_overshoot entries. Furthermore, he illustrated typ, min, and maximum thresholds and their relationship to a Vth threshold voltage. Bob Ross commented later that pending BIRD62.6 may cover much, if not all of these details. The S_overshoot and D_overshoot parameters are defined for currents that are transformed into voltages for a variety of clamping conditions that are appropriate for the technology. Clamping conditions range from no clamp, leakage currents, regular clamp and zener clamp. Some recommendations are provided for assuring that table data points are spaced for maximum accuracy. The changes in slow need to be with 3 to 4 percent of the previous slope. Load conditions for [Rising Waveform] and [Falling Waveform] are given. Also, if the overshoot exceeds 10 percent, [Driver Schedule] is recommended. A number of topics are not covered in this draft, but are expected to be included in the future. The include [Driver Schedule], [TTgnd], [TTpower], terminations and passive series elements, [Series MOSFET], [Submodel]s, .pkg and .ebd formats. Gerald introduced additional parameters needed for the internal Siemens tool called Logical Design Rule Checking (LDRC). This tool performs design checks for connectivity, reasonableness, power, etc. that are normally not included in EDA tools. For example, the keyword [SI_add_pin_info] documents more information for each pin: clock (clock, latch, asynchronous Set/Reset inputs) data (data/address inputs, synchronous Set/Reset inputs) logic (buffer and other combinational inputs) static (enable inputs, control inputs) Vbb for ECL) vsource (built in voltage source such as analog (crystal, R/Cext, OpAmp inputs and outputs) pwr_gnd (Vcc, Gnd, Vee) dnc (physically exiting, but not connected nnc (pin does not exist) unknown (assignment to one of the above not possible) output (all outputs) Gerald discussed the [SI_add_cell_information] keyword. It would give ioh_max, ioh_min, bushold min and max currents, technology, and leakage current limits. Furthermore it would define input slew rate limits. Gerald answered in response to a question from Tom Dagostino that the input slew rate also covered reflected wave switching. Technology information relates to actual driver application such as bus driver, board and back plane application, shortest cable connections. Also hot insertion rules are indicated, if allowed. Also, EOS robustness is of concern. The [SI_analog_model] keyword gives c_subst, r_subst_ and v_substr values. Gerald noted that Siemens simulates 100 percent of the boards and 100 percent of the nets. During and after the presentation, number of these items were discussed. Werner Rissiek commented that the additions could be pushed through the IBIS committee. TIPS AND TRICKS FOR CREATING IBIS MODELS Cary Mandel, Innoveda (formerly Viewlogic Systems) Cary Mandel commented that Jon Powell of Innoveda Consulting Services wrote this. The material was based on experiences producing IBIS models from HSPICE and testing them on an Innoveda simulator. The overall test setup is part of an internal Virtual Modeling Lab (VML) which allows programming of extraction and test conditions. Cary showed the preferred 50 ohms to ground and 50 ohms to Vcc loads for extracting V-T tables. Package parasitics need to be removed. Cary noted that Spice options need to be set for proper DC convergence, and that the time response needs to be long enough to reach the final value. Sometimes the IBIS 100 point limit makes it difficult to have high accuracy for typ, min and max columns simultaneously. Cary also noted that the input signal should be fast enough so that does not slow down the output response. To do the quality assurance (QA) comparisons, a mid point voltage needs to be selected to synchronize the rising and falling edges. Then results can be overlayed and compared. To further test the model, comparisons using other test conditions such as 50 pF to ground, a transmission line load, and a full package test case could be added. Cary listed some common problems: Simulation time does not allow waveform to reach full high or low. Spice model does not behave well at the corners. Spice models need special control options to converge. Spice diode models create unlikely amounts of current. QA simulation does not reproduce some Spice features. The difficulties with IBIS are: 100 point limit can create difficulties in fitting large typ, min, and max I-V and V-T tables. Careful linearization may be needed. Typ, Min and Max may not describe full range of corners desired. The LC package model may be insufficient. The IBIS Version 3.2 T-line model is needed in many cases including RAMBUS modeling. The transition time (ramp) is not very useful for rise time controlled and many high speed advanced drivers. Cary showed an example of a QA simulation where a model with V-T waveforms overlayed the source data compared to the one based on ramp data with a significant time mismatch. Tom Dagostino commented on his experiences measuring diode currents and suggested a limit in the order of 100 mA to 1 A. Default generic diodes were suggested when the Spice model contains unrealistic "ideal diodes". IBIS ACCURACY STUDY Sherif Hammad, Mentor Graphics Sherif Hammad introduced some metrics for comparing model simulation results with initial time waveform extractions. The first two dealt with delay comparison and alignment and the last three dealt with accuracy comparisons: CCPV - Cross-Correlation Peak Value CCTO - Cross-Correlation Time Offset AAD - Average Absolute Difference in V AAD (%) - Average Absolute Difference in percentage COM (%) - Curve Overlay Metric (from the Accuracy Specification) Then Sherif illustrated the metrics with IBIS Models constructed using four waveforms (50 ohms to ground and Vcc), two waveforms (50 ohms to ground for rising and 50 ohms to Vcc for falling), and then ramp specification for the same conditions. The illustrations and metrics showed nearly perfect correlation (99.8%) for the four waveform cases, and worse correlation for the two waveform (96.0% to 98.2%) and ramp (97.5%) cases. The delay metrics showed nearly zero shift for the best four waveform cases, and up to 100 picoseconds for some other cases. Then Sherif illustrated testing the robustness of the four waveform based model using a 50 ohm to Vcc/2 load (99.5%) and 30 ohm to ground load (99.2%). The delay shift was up to 10 picoseconds. This was just a sampling of tests. Lionel Dreux commented that he needed to match IBIS Model loads to the actual net loads for accuracy. After some clarification discussion, we determined that the best model was still based on resistive loads (not timing) loads and that Sherif's results showed good accuracy. However, Fabrice Boissiere and others commented that different technologies might require different loads consistent with their typical operating conditions (for example, GTL uses 25 ohms to 1.0 V). TC93WG6 EMC/EMI IC MODEL STANDARDIZATION REPORT Jean-Claude Perrin & Jean-Yves Oberle, Texas Instruments Jean-Claude Perrin, chair of IEC TC93WG6 introduced the EMC/EMI simulation needs: IC manufacturers need to take into account EMC constraints in IC design and need to simulate EMC behavior and contribution PCB manufacturers need to comply with EMC requirements and simulate EMC phenomena on PCBs. Jean-Claude summarized the history of the committee. It began work in 1994, introduced IEC 93/67 NP in June 1997, held an international task force meeting in 1998, and held a recent experts meeting on March 30, 2000. The main conclusion is that IBIS Models can be enhanced to do top-level EMI simulation. IBIS does not take into account: I/O noise due to internal activity Fast transitions of current through power supplies Direct electromagnetic emission from ICs At this time the task group is concerned with emission and not susceptibility. A model for behavioral simulation was shown. It consists of: Zp and Ip impedance current and noise generator across the Vdd/Vss supplies, Sa and Ga equivalent noise generator/antenna responsible for external hf noise emission, Hx(F) transfer functions between internal generator and other input/output pins. The active blocks are: Core power supplies Peripheral (I/O) power supplies Clock signals activity Package A draft proposal for IBIS format extension consists of these new keywords: [Core Current] Instantaneous current consumption [Pad Current] Instantaneous current consumption [Die Size] Width and length of the die [Clock Frequency] Clock frequencies of the device [Pad Clock] List of pads connected to one of the clocks The proposal is still in draft form and has not been made available outside of the committee. Jean-Claude outlined some of the remaining steps. IEC and the IBIS Open Forum would look at the document and assist in model validation and vote on the document. The document needs to show: Model definition Tem cell current measurement IBIS EMC specific files Jean-Claude proposes that EDA vendors assist in validating the model adapting their tools to do simulation of power supply and clock signals. Jean-Yves Oberle showed measurements of the electric field radiated by an IC for two orientations shifted 90 degrees apart. Jean-Yves compared the measurements to simulation results. The shapes showed excellent agreement, but noted that measurement setup variables are hard to control, and the simulation used approximations. Jean-Yves highlighted areas where the differences were 15 dB to 25 dB, still not bad for this type of comparison. A number of technical question and suggestions were discussed. Jean-Yves explained that the simulation was performed using Maxwell equations and Spice. Werner Rissiek liked the model. Jean-Claude noted that a different group, IEC TC47 is working on measurement standards. Tom Dagostino asked how long the simulation took and suggested a simpler test case, such as a wire, when the response was about one day. Based on his experiences, Lionel Dreux suggested that closer simulations results might be achieved by also considering magnetic sources. This type of simulation needs to include the decoupling network on PCBs. Bob Ross commented that the document needs to be released for public distribution in order for it to proceed. Jean-Claude intends to work on the refinements and then have it made available to the IBIS Open Forum. Later in the meeting Bob stated that the draft document was structured as a Section 10 addition to IBIS Version 3.2. This might be a good way to go since IBIS Version 3.2 is stable. (Bob had considered having this as a separate stand-alone standard to make it easier to ratify.) IBIS FUTURE ACTIVITIES Bob Ross, Mentor Graphics Bob Ross moved his presentation to the time slot before lunch. Bob gave an overview of the meeting today. It deals with current and future specification requirements and clarification, modeling tips and accuracy studies. It also deals with potential future activities including the EMI/EMC modeling, behavioral receiver modeling, and the current IBIS development activities. Bob gave a status update showing that IBIS Version 3.2 is now an official ANSI/EIA-656A standard and is approved as IEC 62014-1 and is awaiting publication. The ibischk3.2.5 parser has been released, but some bugs have been discovered and need to be fixed. The IBIS Users group has released the IBIS Connector Specification to the IBIS Open Forum Committee and also may be resuming work on the Accuracy Specification. The Accuracy Specification is now targeted to be a handbook. The IBIS Open Forum chose not to produce a Spice to IBIS for IBIS Version 3.2 since commercial vendors are also interested in doing this. The main activities of the IBIS Open Forum are The Connector Specification IBIS Version 4.0 IBIS-X for the future The IBIS Open Forum continues to track other activities: TC93WG6 EMC/EMI EIAJ IMIC Specification JEDEC activities Bob summarized some technical aspects of the Connector Specification and noted that after a syntax review, a formal review leading to a ratification vote will be conducted. The Specification is expected to be ratified around mid 2000 as a Version 1.0 document and then a syntax checker and parser development project is expected to be initiated. The IBIS Version 4.0 update is driven by some immediate needs by the JEDEC for DDR memories and current SSTL-3 technologies. BIRD62.6 is expected to be ratified for better input specification detail. Dr. Bernhard Unger's solution for simultaneous switching noise (SSN) modeling is of great interest. Other open BIRDs and specification suggestions will be examined. Perhaps a few other ideas such as AVC modeling might be proposed and considered. This upgrade is expected to be ratified sometime during 2000. The IBIS-X activity is really a name for a group of possible proposals that relate to longer term needs for IBIS. Many needs have been reported on the IBIS reflector and at several of the recent IBIS Summit Meetings. The latest meeting held January 31, 2000 contained several presentations that covered IBIS-X, "BIRDxxx", macro language, application programmable interface and other ideas. Bob noted from one presentation that there was interest in scalability (one node to many nodes), flexible representation (current IBIS elements, controlled voltage and current sources, S-parameters, etc.), and nodal representation similar to Spice. Bob also reported that the IBIS-X proposal might be similar and support much of IBIS. It might also support functional port definitions and also some Spice-like nodal constructs. This would allow faster production of models as technological advances occur. (Later, Bob noted that Werner Rissiek had suggested that IBIS-X may be moving towards becoming a modeling language (such as Spice) as opposed to a format for model data. Bob reported that several people planned to meet in Oregon on Thursday, March 30, 2000 to start formulating a consensus proposal. Bob expected that while we may see the proposal shortly, we may take a year or two for actual review and ratification as a separate standard. BEHAVIORAL RECEIVER MODELING Patrick Dos Santos, Cadence Design After a delicious buffet lunch hosted by Cadence Design, Patrick Dos Santos indicated that the Behavioral Receiver Modeling presentation was authored by Donald Telian and had also been given at the January 31, 2000 IBIS Summit Meeting. Patrick showed the evolution of design methodology: Use terminations (mid-1980s) Driver scaling and tuning (early 1990s leading to IBIS and to tools for topology optimization) Now - more detailed receiver modeling Receiver modeling allows optimization: What switching functions are needed? What type of pulses are to be rejected? What sort of propagation characteristics will work? What voltages should this all operate at? The best approach is to use a nodal behavioral description because it allows modeling of a receiver's characteristics and also is easily adaptable to arbitrary behaviors. Patrick noted that nodal based receivers can be derived from measurement or simulation. The behavioral receiver contains these blocks: #1: Low Pas filter - reject certain pulse spikes #2: Switching Function - receivers basic transfer function #5: Intrinsic Delay - delay for fasted edge #3: Edge Rate Detection - derivative of input signal affects delay #4: Delay Adder - dynamically adjusts circuit delay based on #3 Its implementation needs these features: Nodal language G (VCC) and E (VCVS) sources (PWL, Equation driven with derivatives, even driven and time-controlled as well) Real-time adaptive delay line Subcircuiting nesting and random node printing Based on 242 difficult test cases, the simulation results showed an average difference of 19 pS (standard deviation of 14 pS). Simulation times were slightly slower, but still in the same order of magnitude as Spice simulations. Many of the models had additional proprietary elements, slowing the simulation. Gerald Bannert asked whether input impedance details can be accurately modeled. Patrick responded yes since input elements can be added to any level of detail using standard nodal syntax. Also differential inputs and clamping diodes can be modeled. Lionel Dreux commented that the approach might be extended for field coupling to a PCB. It might be used for susceptibility. Upon questioning, Patrick stated that non-linear effects are included. Werner Rissiek commented that the IBIS still has its place since it is scalable to any accuracy needed. For example, the IBIS model can be as simple or detailed as appropriate for the analysis. Patrick stated that the behavioral receiver model could be scalable. CLOSE OF MEETING Bob Ross provided some more detail on the pending Connector Specification regarding using cascaded sections to configure the connector for different sockets and different board thicknesses (for the edge card side of an edge card connector). Bob summarized that along with current activities dealing with the Connector Specification, IBIS Version 4.0 definition and IBIS-X definition, the IBIS Open Forum could also be dealing with more IBIS Version 3.2 clarifications based on the Siemens requirements, possible electronic data sheet requirements needed by Siemens, and possibly an EMI Section 10 addition to IBIS Version 3.2. Bob again thanked the participants for their contributions and the co-sponsors. Several participants commented on the amount of interesting material presented at this meeting and supported IBIS as an appropriate level for the potential extensions. NEXT MEETING: The next teleconference meeting will be on Friday, April 14, 2000 from 8:00 AM to 10:00 AM. BIRD62.6 will be scheduled for voting. ============================================================================== NOTES IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897 bob_ross@mentor.com Modeling Engineer, Mentor Graphics 8005 S.W. Boeckman Road, Wilsonville, OR 97070 VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515 sjpeters@ichips.intel.com Senior Hardware Engineer, Intel Corporation M/S JF1-209 2111 NE 25th Ave. Hillsboro, OR 97124-5961 SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259 gdeburgh@innoveda.com Senior Manager, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 LIBRARIAN: Jon Powell (805) 988-8250, Fax: (805) 988-8259 jpowell@innoveda.com Senior Scientist, Innoveda 1369 Del Norte Rd. Camarillo, CA 93010-8437 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Signal Integrity Engineer, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Matthew Flora (425) 869-2320, Fax: (425) 881-1008 mbflora@hyperlynx.com Senior Engineer, HyperLynx, Inc. 114715 N.E. 95th Street Redmond, WA 98052 This meeting was conducted in accordance with the EIA Legal Guides and EIA Manual of Organization and Procedure. The following e-mail addresses are used: ibis-request@eda.org To join, change, or drop from either the IBIS Open Forum Reflector (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org) or both. State your request. ibis-info@eda.org To obtain general information about IBIS, to ask specific questions for individual response, and to inquire about joining the EIA-IBIS Open Forum as a full Member. ibis@eda.org To send a message to the general IBIS Open Forum Reflector. This is used mostly for IBIS Standardization business and future IBIS technical enhancements. Job posting information is not permitted. ibis-users@eda.org To send a message to the IBIS Users' Group Reflector. This is used mostly for IBIS clarification, current modeling issues, and general user concerns. Job posting information is not permitted. ibischk-bug@eda.org To report ibischk2/3 parser bugs. The Bug Report Form Resides on eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs. To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt respectively. Information on IBIS technical contents, IBIS participants, and actual IBIS models are available on the IBIS Home page found by selecting the Electronic Information Group under: http://www.eia.org/eig/ibis/ibis.htm Check the pub/ibis directory on eda.org for more information on previous discussions and results. You can get on via FTP anonymous. ==============================================================================