AGENDA, EUROPEAN IBIS SUMMIT MEETING
Friday, May 13, 2014
Seminaris Campus Hotel Berlin/ Dahlem Cube
Takustraße 39, 14195
Berlin, Germany
Room: Cambridge (Check at Entrance)
Sponsored by ANSYS, CST, Mentor Graphics Corporation, Synopsys, Zuken
(order and times subject to change)
13:00 Sign In
13:15 WELCOME AND INTRODUCTIONS
Randy WOLFF, Micron Technology, IBIS Secretary, USA
13:30 Physics and Modeling of Vias in Printed Circuit Boards
Jan PREIBISCH and Christian SCHUSTER,
Technische Universitat Hamburg-Harburg, Germany
[Presented by Jan PREIBISCH]
14:30 Chair's Status Report (.zip)
Michael MIRMAK, Intel Corporation USA
[Presented by Randy WOLFF, Micron Technology, USA]
15:00 IBIS Model Formulation and Extraction for SPI Evaluation
Wael DGHAIS, Kevin F.G. PINTO, and Jonathan RODRIGUEZ;
University of Averio, Institute of Telecommunications,
Portugal
[Presented by Wael DGHAIS]
15:30 BREAK (15 Minutes)
15:45 [Define Package Model] Proposed Extension
Randy WOLFF*, Radek BIERNACKI**, and Bob ROSS***,
*Micron Technology, **Keysight Technology, and ***Teraspeed Labs, USA
[Presented by Randy WOLFF]
16:15 Interconnect Task Group Update - Package Modeling
Randy WOLFF, Micron Technology, USA
16:45 Time Response Utility (.xls) (.zip)
Bob ROSS, Teraspeed Labs, USA
[Presented by Anders EKHOLM, Ericsson, Sweden]
17:15 SSO Experience with IBIS
Manfred MAURER, IT-Beratung-Maurer, Germany
[Presented by Manfred MAURER]
17:45 DISCUSSION AND CLOSING REMARKS
Randy WOLFF, Micron Technology, USA
18:00 END OF MEETING
People involved in IBIS Model development, EDA tool development, and digital circuit design are invited to participate to the Summit meeting. If you plan to participate, please register with the information below:
Name: E-mail address: Company:
Send to: Lance WANG (lwang@iometh.com)
See http://www.spi2015.org/ for travel directions, IBIS meeting hotel and other information.