------------------------------------------------------------------

               AGENDA, EUROPEAN IBIS SUMMIT MEETING              
                     Wednesday, May 11, 2016

                       STARHOTEL MAJESTIC
                Corso Vittorio Emanuele II, 54
                         Turin, Italy
                                    
           Room: Vittoria A/B (main conference room)

      Agenda Link: http://www.spi2016.org/program_wed.asp

------------------------------------------------------------------

13:45  SIGN IN, REFRESHMENTS

14:00  WELCOME AND INTRODUCTIONS
         Lance WANG, IO Methodology, IBIS Vice-chair, USA

14:10  IBIS Update
         Mike LABONTE*, Lance WANG**
         *Signal Integrity Software (SiSoft),
         **IO Methodology; USA
         [Presented by Lance WANG]

14:20  Understanding IBIS-AMI Simulations
         Richard ALLRED
         Signal Integrity Software (SiSoft), USA

14:50  Using IBIS-AMI Models to Maximize Data Rate Given SerDes
       EQ and Channel ISI/Loss
         Donald TELIAN, SiGuys; USA

15:20  Initial Delay Issues in Analog IBIS Buffers
         Michael SCHAEDER, Mariusz FAFERKO, Amir WALLRABENSTEIN
         Zuken; Germany

15:40  IBIS + Mpilog: Current and Future Developments on I/O
       Buffer Modeling
         Gianni SIGNORINI*#, Claudio SIVIERO**##,
         Igor Simone STIEVANO**##, Stefano GRIVET-TALOCIA**##,
         Michael MIRMAK*###
         *Intel Corporation, **Politecnico di Torino;
         #Germany, ##Italy, ###USA
         [Presented by Gianni SIGNORINI]

16:10  BREAK, REFRESHMENTS (15 Minutes)

16:25  Models for IC Buffers: A Top-down Approach
         Cherif DIOUF*#, Mihai TELESCU**#, N. TANGUY**#,
         Igor Simone STIEVANO***##, Flavio G. CANAVERO***#
         *Ecole Nationale d'Ingeniurs de Brest,
         **Universite de Bretagne Occidentale,
         ***Politecnico di Torino;
         #France, ##Italy
         [Presented by Mihai TELISCU] 

16:55  Multiport I/O Model Computation for Power-Aware SI
       Simulation
         Wael DGHAIS* and Fethi BALLAMINE**
         *University of Soursse, **Universite de Carthage;
         Tunisa
         [Presented by Wael DGHAIS]

17:35  On-Die Decoupling Model Improvements for IBIS Power Aware
       Models
         Randy WOLFF#, Aniello VISCARDI##
         Micron Technology; #USA, ##Italy
         [Presented by Randy WOLFF]

17:55  CLOSING REMARKS
         Lance WANG, IO Methodology, IBIS Vice-chair, USA

18:00  END OF MEETING

------------------------------------------------------------------

REGISTRATION INFORMATION

People involved in IBIS Model development, EDA tool development,
and digital circuit design are invited to participate to the
Summit meeting. If you plan to participate, please register with
the information below:

   Name:
   E-mail address:
   Company:

Send to:

   Lance WANG (lwang@iometh.com)

SPONSORS:

   ANSYS
   CST
   Keysight Technologies
   Synopsys
   Zuken

SPI CONFERENCE INFORMATION AND TRAVEL DIRECTIONS

   See http://www.spi2016.org/ for travel directions,
   IBIS meeting hotel and other information.

------------------------------------------------------------------