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               S U M M I T   I N F O R M A T I O N

Time/Date:  9:00 - 17:00, Friday November 14, 2008

Location:   JEITA Headquarters (New Location)
            Chiyoda First Bldg. South Wing, 3-2-1
            Nishi-Kanda, Chiyoda-ku
            Tokyo, 101-0065
            JAPAN

            http://www.jeita.or.jp/english/about/location/index.htm

Registration:  FREE, send to both addresses below:
            Name:
            E-mail address:
            Company:
            Telephone:

   Bob ROSS, Teraspeed Consulting Group    bob@teraspeed.com
   Kazuyoshi SHOJI, Hitachi ULSI Systems   kazuyoshi.shohji.aj@hitachi.com

Organizational Sponsors:
            Japan Electronics and Information Technology Industries
               Association (JEITA)
            EIA IBIS Open Forum

Co-Sponsors: (in alphabetical order)
            Agilent Technologies
            Ansoft
            ATE Service Corporation (Sigrity)
            Cadence
            Cybernet Systems
            Fujitsu
            Zuken

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          I B I S  S U M M I T  M E E T I N G  A G E N D A

09:00   REFRESHMENTS & SIGN IN
          - Vendor Tables Open

09:30   General Announcement
          Shoji, Kazuyoshi (Hitachi ULSI Systems, JAPAN)

09:35   Meeting Welcome
          Watanabe, Takashi (NEC Electronics Corp. and JEITA, Japan)
          Mirmak, Michael (Intel Corporation, USA)

09:45   Japan IBIS Activities Update
          Shoji, Kazuyoshi (Hitachi ULSI Systems, Japan)
        
09:55   Micron's IBIS Model Quality Process
          Wolff, Randy (Micron Technology, USA)

10:25   IBIS Quality Activities in JEITA EDA WG 
          Hamaji, Yoshihiro (Toshiba I.S. Corporation, Japan)

10:50   BREAK (Refreshments)
          - Vendor Tables

11:10   Look into IBIS Buffer Curves
          Wang, Lance (IO Methodology, USA)

11:35   Easy Use of IBIS Model with Simulation Kit
          Matsuzawa, Hirohiko (Zuken, Japan)

12:05   New Table-based Keywords in IBIS 5.0, A Cookbook-style Guide
          Mirmak, Michael (Intel Corporation, USA)

12:30   FREE BUFFET LUNCH (Hosted by Sponsors)
          - Vendor Tables

13:15   Touchstone 2.0 Mixed-Mode Syntax - Updated
          Ross, Bob (Teraspeed Consulting Group, USA)

13:45   IBIS EBD Modeling, Usage and Enhancement, An Example
        of Memory Channel Multi-board Simulation
          Xu, Tao (Sigrity, China)
          [Presented by Honda, Yutaka (ATE Service Corporation
          (Sigrity), Japan]

14:15   De-emphasis Buffer Modeling Issues with IBIS
          Rao, Nanditha (Intel Corporation, India)

14:45   Eye Masks in IBIS
          Meng, YuBao (Cadence Design Systems, China)
          [Presented by Masuko, Yukio (Cadence Design Systems, Japan)]

15:05   BREAK (Refreshments)
          - Vendor Tables

15:35   System-level Serial Link Analysis using IBIS-AMI Models
          Westerhoff, Todd (Signal Integrity Software (SiSoft), USA)
          [Presented by Wang, Lance (IO Methodology, USA)]

16:05   Noise Countermeasure Design Technology for Signal and Power
        Integrity
          Sato, Toshiro (Fujitsu Advanced Technology, Japan)

16:35   Open Discussions

16:55   Concluding Items

17:00   END OF MEETING (POST-SUMMIT REFRESHMENTS)
  
              
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