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       A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

Time/Date:  8:15 - 17:30, Tuesday November 9, 2010

Location:   Four Points by Sheraton
            5 Guihua Road
            Futian Free Trade Zone
            Shenzhen, Guangdong 518038
            P. R. China

Rooms:      Shenzhen A   (Look for signs)

Sponsors:   Huawei Technologies (Primary)
            Agilent Technologies
            Ansoft
            Cadence Design Systems
            Cybernet Systems
            Intel Corporation
            IO Methodology
            Mentor Graphics Corporation,
            Signal Integrity Software (SiSoft)
            Sigrity
            Synopsys
            ZTE Corporation

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          I B I S  S U M M I T  M E E T I N G  A G E N D A

8:15    REFRESHMENTS & SIGN IN
         - Vendor Tables Open at 8:30

9:15    Welcome
         - Li, JinJun
           (Huawei Technologies, China)
         - Mirmak, Michael
           (Chair, IBIS Open Forum, Intel Corporation, USA)

9:35    Point Reduction Method for IBIS Curves
          Wang, Lance (IO Methodology, USA)

10:05   BREAK (Refreshments and Vendor Tables)

10:25   IBIS for SSO Analysis
          Wang, HaiSan; Luo, Joshua; Lin, Jack; and Zhong, ZhangMin
          (Sigrity, China)

11:05   PDN Design and Analysis Methodology in SI&PI Co-design
          Luo, ZiPeng and Liu, SuYao (Huawei Technologies, China)

11:35   Correlating C_pin Capacitance with Measurements
          Wolff, Randy (Micron Technology, USA)

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)
          - Vendor Tables

13:30   Automated AMI Model Generation & Validation
          Pino, Jose Luis*; Badesha, Amolak*; Luschas, Manuel**;
          Orpahanou, Antonis**; and Civit, Halil**
          (*Agilent Technologies and **NetLogic Microsystems, USA)

14:10   Spice Subcircuit Support for Serial Link Channel Design
        Using IBIS [External Model]
          Dong, XiaoQing*; Zhong, ZhangMin**#; and Willis, Ken**##
          (*Huawei Technologies, China and **Sigrity, #China, and ##USA)

14:40   Extending/Leveraging IBIS Constructs to Model High-Speed
        I/Os and Packages using AMI, Spice, and S-Parameters
          Lin, John*, Al-Hawari, Feras**##, Kukal, Taranjit**#, and
          Varma, Ambrish**## (*Flextronic, China, and
          **Cadence Design Systems, #India and ##USA)

15:10   BREAK (Refreshments and Vendor Tables)

15:30   IBIS-ISS: What Is It and What It Means to You
          Mirmak, Michael (Intel Corporation, USA)

16:00   Modeling Methods for Complex S-parameters in Touchstone 2.0
          Guan, JinKu and Zhu, Shunlin (ZTE Corporation, China)

16:30   Model Connection Protocol Extensions for Mixed Signal SiP
          Kukal, Taranjit*#; Dai, WenLiang*##; Brim, Brad**; and
          Fujine, Eiji***
          (*Cadence Design Systems, #India, ##China, **Sigrity, USA and
          ***Fujitsu VLSI Limited, Japan)

17:00   Concluding Items

17:30   END OF IBIS SUMMIT MEETING

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