------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: 8:15 - 17:30, Tuesday November 15, 2011 Location: Parkyard Hotel Shanghai 699 Bibo Road Zhangjiang Hi-Tech Park Shanghai 201203 P.R. China Rooms: Ballroom ABC (Look for signs) Sponsors: Huawei Technologies (Primary) Agilent Technologies ANSYS Cadence Design Systems Intel Corporation IO Methodology Sigrity Synopsys ZTE Corporation ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:15 REFRESHMENTS & SIGN IN - Vendor Tables Open at 8:30 8:45 Welcome - Li, JinJun (Huawei Technologies, China) - Mirmak, Michael (Chair, IBIS Open Forum, Intel Corporation, USA) 9:00 IBIS Status and Future Direction Mirmak, Michael (Intel Corporation, USA) 9:15 IBIS Model as De-Facto Standard Kusunoki, Kazuhiko* and Dai, WenLiang** (*Wadow Co., Japan and **Xpeedic, China) 9:40 IBIS VT Waveform and Over Clocking Chen, XueFeng (Synopsys, China) 10:10 BREAK (Refreshments and Vendor Tables) 10:30 IBIS Parsers Ross, Bob (Teraspeed Consulting Group, USA) 11:00 DDR3 System Timing Budget Analysis by SI&PI Co-Simulation Yi, Bi; Wang, Ping; and Zhu, Shunlin (ZTE Corporation, China) 11:30 Modeling the On-die De-cap of IBIS 5.0 PDN-aware Buffers Wang, Lance* and Wolff, Randy** (*IO Methodology, and **Micron Technology, USA) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) - Vendor Tables 13:30 Power-aware I/O Modeling for High-speed Parallel Bus Simulation Qin, ZuLi#; Wang' HaiSan#; Lin, Jack W.C.#; and Chen, Raymond Y.## (Sigrity, #China, ##USA) 14:05 The Application of of IBIS-AMI Model Cascaded Simulation for 10 Gigabit Repeater Serial Link Analysis Xu, ZhengRong*; Ma, LuYu*; Willis, Ken**#; Wang, HaiSan**##; Sledjeski, Lee***; and Unger, Nate*** (*Huawei Technologies, China, **Sigrity, #USA, ##China, ***Texas Instruments, USA) 14:30 AMI Applications in High-speed Serial Channel Analysis and Measurement Correlation Jia, Wei; Sun, AnBing; and Zhu, ShunLin (ZTE Corporation, China) 15:00 BREAK (Refreshments and Vendor Tables) 15:20 Pseudo Transient Eye Analysis by Convolution Method Li, BaoLong (ANSYS, China) 15:45 Introduction of FEC IL Gain Estimation Method in High Speed Link Dong, XiaoQing and Huang, ChunXing (Huawei Technologies, China) 16:15 Supporting External Circuit as Spice or S-parameters in Conjunction with I-V/V-T Tables Drumstad, Kent*; Hawes, Adge*##; Kukal,Taranjit**###; Al-Hawari, Feras**#; Varma, Ambrish**#; and Jernberg, Terry**# (*IBM, #USA, ##United Kingdom, **Cadence Design Systems, ###India, #USA) 16:50 Board-Only Power Delivery Prediction for Voltage Regulator and Mother Board Designs He, JiangQi# and Li, Y.L.## (Intel, #USA, ##China) 17:25 Concluding Items 17:30 END OF IBIS SUMMIT MEETING ------------------------------------------------------------------