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       A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

Time/Date:  8:15 - 17:30, Tuesday November 9, 2012

Location:   Parkyard Hotel Shanghai
            699 Bibo Road
            Zhangjiang Hi-Tech Park
            Shanghai 201203
            P.R. China

Rooms:      Ballroom ABC   (Look for signs)

Sponsors:   Huawei Technologies (Primary)
            Agilent Technologies
            ANSYS
            Cadence Design Systems
            Intel Corporation
            IO Methodology
            Synopsys
            Teledyne LeCroy
            ZTE Corporation

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          I B I S  S U M M I T  M E E T I N G  A G E N D A

8:15    SIGN IN
         - Vendor Tables Open at 8:30

8:45    Welcome
         - Li, JinJun
           (Huawei Technologies, China)
         - Wang, Lance (Vice-Chair IBIS Open Forum),
           (IO Methodology, USA)

9:00    IBIS 5.1: An Overview
          Mirmak, Michael (Intel Corporation, USA)

9:25    Using Latency Insertion Method to Handle IBIS Models
          Liu, Ping*#; Tan, Jilin*##; and Schutt-Aine, Jose**
          (*Cadence Design Systems, #China, ##USA; and
          **University of Illinois, USA)

10:00   BREAK (Refreshments and Vendor Tables)

10:25   Channel Simulation Platform Creation in Matlab and IBIS-AMI
        Simulation Verification
          Liu, Jason*; Xue, Harrison*; and Yan, Benny**
          (*Celestica and **Cadence Design Systems, China)

10:50   Effect Analysis of IL Resonance between 0.5~1 Normalized
        Frequency Bandwidth
          Huang, ChunXiang; Dong, XianQing; and Yu, Lan
          (Huawei Technologies, China)

11:20   Efficient End-to-end Simulations of 25G Optical Links
          Liu, Jing-Tao*#; Rao, Fangyi*##; Gupta, Sanjeev**; and
          Badesha, Amolak**
          (*Agilent Technologies, #China, ##USA; and
          **Avago Technologies, USA)

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)
          - Vendor Tables

13:30   Analysis of the Impact of Crosstalk in High-Speed Serial
        Links
          Sun, AnBing; Yin, ChangGang; and Jia, Wei
          (ZTE Corporation, China)

14:00   Verification of ICN Usability in Characterizing System
        Crosstalk
          Dong, XiaoQing; and Huang, ChunXiang
          (Huawei Technologies, China)

14:30   Chip PDN Model for Power Aware Signal Integrity Analysis
          Lin, Jack W.C.#; and Chen, Raymond Y.##
          (Cadence Design Systems, #China, ##USA)
         
15:00   BREAK (Refreshments and Vendor Tables)

15:25   IBIS Parser Update
          Ross, Bob (Teraspeed Consulting Group, USA)

15:50   IBIS Validation Method Review
          Wang, Lance (IO Methodology, USA)

16:15   The Evolution of DDR Memory and Overcoming Challenges of
        DDR3/4 Design
          Pytel, Steven (ANSYS, USA)

16:45   Designing DDR3 System Using Static Timing Analysis in
        Conjunction with IBIS Simulations
          Kukal, Taranjit#; Zhong, ZhangMin##; and Dudek, Heiko###
          (Cadence Design Systems, #India, ##China, ###Germany)

17:25   Concluding Items

17:30   END OF IBIS SUMMIT MEETING


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